#
1.13 |
|
07-Aug-2021 |
jmcneill |
arm: acpi: Add support for SMCCC based PCI config access.
|
Revision tags: thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 cjep_staticlib_x-base thorpej-i2c-spi-conf-base thorpej-cfargs-base thorpej-futex-base
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#
1.12 |
|
07-Dec-2020 |
jmcneill |
acpicpu: Add support for ACPI P-states and T-states on Arm.
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#
1.11 |
|
10-Oct-2020 |
jmcneill |
branches: 1.11.2; Support early FB console attachment when booting with a devicetree (non-ACPI mode). Inform the pciconf code about the framebuffer to prevent pciconf from changing resources out from under us when framebuffer memory is in VRAM.
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
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#
1.10 |
|
01-Feb-2020 |
jmcneill |
Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
#
1.9 |
|
17-Jan-2020 |
jmcneill |
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around: - PCIe root port config space lives in a non-standard location. - Access to PCIe config space of devices that do not exist results in an sync SError. Firmware creates a "known devices" table at a fixed physical address that we use to filter PCI conf access to only known devices.
This change splits the Arm ACPI PCI quirks into separate files for each host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to multi-segment support. The MI ACPI PCI code was using a shared PCI chipset tag to access devices, and these accesses can happen before our PCI host bridge drivers are attached! The global chipset tag is now gone, and an MD callback can provide a custom tag on a per-segment basis.
|
Revision tags: ad-namecache-base phil-wifi-20191119
|
#
1.8 |
|
14-Oct-2019 |
jmcneill |
branches: 1.8.2; Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
|
#
1.7 |
|
22-Sep-2019 |
jmcneill |
Use vcons for simplefb preattach to speed up early console messages.
|
Revision tags: netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226
|
#
1.6 |
|
08-Dec-2018 |
jmcneill |
branches: 1.6.4; 1.6.6; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
|
Revision tags: pgoyette-compat-1126
|
#
1.5 |
|
12-Nov-2018 |
jmcneill |
Support building kernels with ACPI and no PCI.
|
#
1.4 |
|
24-Oct-2018 |
jmcneill |
Add driver for ARM Server Base System Architecture (SBSA)-compliant generic watchdog timers.
|
#
1.3 |
|
21-Oct-2018 |
jmcneill |
Add GICv3 ACPI attachment glue.
|
Revision tags: pgoyette-compat-1020
|
#
1.2 |
|
15-Oct-2018 |
jmcneill |
branches: 1.2.2; Add ARM ACPI PCI support.
|
#
1.1 |
|
12-Oct-2018 |
jmcneill |
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer, SBSA UART).
|
#
1.12 |
|
07-Dec-2020 |
jmcneill |
acpicpu: Add support for ACPI P-states and T-states on Arm.
|
Revision tags: thorpej-futex-base
|
#
1.11 |
|
10-Oct-2020 |
jmcneill |
Support early FB console attachment when booting with a devicetree (non-ACPI mode). Inform the pciconf code about the framebuffer to prevent pciconf from changing resources out from under us when framebuffer memory is in VRAM.
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
#
1.10 |
|
01-Feb-2020 |
jmcneill |
Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
#
1.9 |
|
17-Jan-2020 |
jmcneill |
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around: - PCIe root port config space lives in a non-standard location. - Access to PCIe config space of devices that do not exist results in an sync SError. Firmware creates a "known devices" table at a fixed physical address that we use to filter PCI conf access to only known devices.
This change splits the Arm ACPI PCI quirks into separate files for each host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to multi-segment support. The MI ACPI PCI code was using a shared PCI chipset tag to access devices, and these accesses can happen before our PCI host bridge drivers are attached! The global chipset tag is now gone, and an MD callback can provide a custom tag on a per-segment basis.
|
Revision tags: ad-namecache-base phil-wifi-20191119
|
#
1.8 |
|
14-Oct-2019 |
jmcneill |
branches: 1.8.2; Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
|
#
1.7 |
|
22-Sep-2019 |
jmcneill |
Use vcons for simplefb preattach to speed up early console messages.
|
Revision tags: netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226
|
#
1.6 |
|
08-Dec-2018 |
jmcneill |
branches: 1.6.4; 1.6.6; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
|
Revision tags: pgoyette-compat-1126
|
#
1.5 |
|
12-Nov-2018 |
jmcneill |
Support building kernels with ACPI and no PCI.
|
#
1.4 |
|
24-Oct-2018 |
jmcneill |
Add driver for ARM Server Base System Architecture (SBSA)-compliant generic watchdog timers.
|
#
1.3 |
|
21-Oct-2018 |
jmcneill |
Add GICv3 ACPI attachment glue.
|
Revision tags: pgoyette-compat-1020
|
#
1.2 |
|
15-Oct-2018 |
jmcneill |
branches: 1.2.2; Add ARM ACPI PCI support.
|
#
1.1 |
|
12-Oct-2018 |
jmcneill |
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer, SBSA UART).
|
#
1.11 |
|
10-Oct-2020 |
jmcneill |
Support early FB console attachment when booting with a devicetree (non-ACPI mode). Inform the pciconf code about the framebuffer to prevent pciconf from changing resources out from under us when framebuffer memory is in VRAM.
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
#
1.10 |
|
01-Feb-2020 |
jmcneill |
Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
#
1.9 |
|
17-Jan-2020 |
jmcneill |
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around: - PCIe root port config space lives in a non-standard location. - Access to PCIe config space of devices that do not exist results in an sync SError. Firmware creates a "known devices" table at a fixed physical address that we use to filter PCI conf access to only known devices.
This change splits the Arm ACPI PCI quirks into separate files for each host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to multi-segment support. The MI ACPI PCI code was using a shared PCI chipset tag to access devices, and these accesses can happen before our PCI host bridge drivers are attached! The global chipset tag is now gone, and an MD callback can provide a custom tag on a per-segment basis.
|
Revision tags: ad-namecache-base phil-wifi-20191119
|
#
1.8 |
|
14-Oct-2019 |
jmcneill |
branches: 1.8.2; Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
|
#
1.7 |
|
22-Sep-2019 |
jmcneill |
Use vcons for simplefb preattach to speed up early console messages.
|
Revision tags: netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226
|
#
1.6 |
|
08-Dec-2018 |
jmcneill |
branches: 1.6.4; 1.6.6; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
|
Revision tags: pgoyette-compat-1126
|
#
1.5 |
|
12-Nov-2018 |
jmcneill |
Support building kernels with ACPI and no PCI.
|
#
1.4 |
|
24-Oct-2018 |
jmcneill |
Add driver for ARM Server Base System Architecture (SBSA)-compliant generic watchdog timers.
|
#
1.3 |
|
21-Oct-2018 |
jmcneill |
Add GICv3 ACPI attachment glue.
|
Revision tags: pgoyette-compat-1020
|
#
1.2 |
|
15-Oct-2018 |
jmcneill |
branches: 1.2.2; Add ARM ACPI PCI support.
|
#
1.1 |
|
12-Oct-2018 |
jmcneill |
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer, SBSA UART).
|
#
1.10 |
|
01-Feb-2020 |
jmcneill |
Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
#
1.9 |
|
17-Jan-2020 |
jmcneill |
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around: - PCIe root port config space lives in a non-standard location. - Access to PCIe config space of devices that do not exist results in an sync SError. Firmware creates a "known devices" table at a fixed physical address that we use to filter PCI conf access to only known devices.
This change splits the Arm ACPI PCI quirks into separate files for each host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to multi-segment support. The MI ACPI PCI code was using a shared PCI chipset tag to access devices, and these accesses can happen before our PCI host bridge drivers are attached! The global chipset tag is now gone, and an MD callback can provide a custom tag on a per-segment basis.
|
Revision tags: ad-namecache-base phil-wifi-20191119
|
#
1.8 |
|
14-Oct-2019 |
jmcneill |
branches: 1.8.2; Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
|
#
1.7 |
|
22-Sep-2019 |
jmcneill |
Use vcons for simplefb preattach to speed up early console messages.
|
Revision tags: netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226
|
#
1.6 |
|
08-Dec-2018 |
jmcneill |
branches: 1.6.4; 1.6.6; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
|
Revision tags: pgoyette-compat-1126
|
#
1.5 |
|
12-Nov-2018 |
jmcneill |
Support building kernels with ACPI and no PCI.
|
#
1.4 |
|
24-Oct-2018 |
jmcneill |
Add driver for ARM Server Base System Architecture (SBSA)-compliant generic watchdog timers.
|
#
1.3 |
|
21-Oct-2018 |
jmcneill |
Add GICv3 ACPI attachment glue.
|
Revision tags: pgoyette-compat-1020
|
#
1.2 |
|
15-Oct-2018 |
jmcneill |
branches: 1.2.2; Add ARM ACPI PCI support.
|
#
1.1 |
|
12-Oct-2018 |
jmcneill |
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer, SBSA UART).
|
Revision tags: ad-namecache-base1
|
#
1.9 |
|
17-Jan-2020 |
jmcneill |
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around: - PCIe root port config space lives in a non-standard location. - Access to PCIe config space of devices that do not exist results in an sync SError. Firmware creates a "known devices" table at a fixed physical address that we use to filter PCI conf access to only known devices.
This change splits the Arm ACPI PCI quirks into separate files for each host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to multi-segment support. The MI ACPI PCI code was using a shared PCI chipset tag to access devices, and these accesses can happen before our PCI host bridge drivers are attached! The global chipset tag is now gone, and an MD callback can provide a custom tag on a per-segment basis.
|
Revision tags: ad-namecache-base phil-wifi-20191119
|
#
1.8 |
|
14-Oct-2019 |
jmcneill |
branches: 1.8.2; Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
|
#
1.7 |
|
22-Sep-2019 |
jmcneill |
Use vcons for simplefb preattach to speed up early console messages.
|
Revision tags: netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226
|
#
1.6 |
|
08-Dec-2018 |
jmcneill |
branches: 1.6.4; 1.6.6; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
|
Revision tags: pgoyette-compat-1126
|
#
1.5 |
|
12-Nov-2018 |
jmcneill |
Support building kernels with ACPI and no PCI.
|
#
1.4 |
|
24-Oct-2018 |
jmcneill |
Add driver for ARM Server Base System Architecture (SBSA)-compliant generic watchdog timers.
|
#
1.3 |
|
21-Oct-2018 |
jmcneill |
Add GICv3 ACPI attachment glue.
|
Revision tags: pgoyette-compat-1020
|
#
1.2 |
|
15-Oct-2018 |
jmcneill |
branches: 1.2.2; Add ARM ACPI PCI support.
|
#
1.1 |
|
12-Oct-2018 |
jmcneill |
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer, SBSA UART).
|