| #
1.7 |
|
15-Oct-2022 |
jmcneill |
Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings
Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
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|
Revision tags: bouyer-sunxi-drm-base thorpej-i2c-spi-conf2-base thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 cjep_staticlib_x-base thorpej-i2c-spi-conf-base thorpej-cfargs-base thorpej-futex-base
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| #
1.6 |
|
24-Oct-2020 |
skrll |
Trailing whitespace
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| #
1.5 |
|
13-Sep-2020 |
jmcneill |
Make Arm MD ACPI code big endian friendly.
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| #
1.4 |
|
17-Jun-2020 |
thorpej |
<sys/extent.h> not needed here.
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| #
1.3 |
|
15-Jun-2020 |
ad |
Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
|
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
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| #
1.2 |
|
13-Feb-2020 |
jmcneill |
branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
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|
Revision tags: ad-namecache-base2 ad-namecache-base1
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| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
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| #
1.6 |
|
24-Oct-2020 |
skrll |
Trailing whitespace
|
| #
1.5 |
|
13-Sep-2020 |
jmcneill |
Make Arm MD ACPI code big endian friendly.
|
| #
1.4 |
|
17-Jun-2020 |
thorpej |
<sys/extent.h> not needed here.
|
| #
1.3 |
|
15-Jun-2020 |
ad |
Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
|
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
|
| #
1.2 |
|
13-Feb-2020 |
jmcneill |
branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
|
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|
| #
1.5 |
|
13-Sep-2020 |
jmcneill |
Make Arm MD ACPI code big endian friendly.
|
| #
1.4 |
|
17-Jun-2020 |
thorpej |
<sys/extent.h> not needed here.
|
| #
1.3 |
|
15-Jun-2020 |
ad |
Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
|
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
|
| #
1.2 |
|
13-Feb-2020 |
jmcneill |
branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
|
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|
| #
1.4 |
|
17-Jun-2020 |
thorpej |
<sys/extent.h> not needed here.
|
| #
1.3 |
|
15-Jun-2020 |
ad |
Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
|
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
|
| #
1.2 |
|
13-Feb-2020 |
jmcneill |
branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
|
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|
| #
1.3 |
|
15-Jun-2020 |
ad |
Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
|
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3
|
|
| #
1.2 |
|
13-Feb-2020 |
jmcneill |
branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
|
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|
| #
1.2 |
|
13-Feb-2020 |
jmcneill |
Enable MSI and MSI-X support on N1SDP
|
|
Revision tags: ad-namecache-base2 ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|
|
Revision tags: ad-namecache-base1
|
|
| #
1.1 |
|
17-Jan-2020 |
jmcneill |
branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.
The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.
This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.
These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
|