#
1.19 |
|
07-Feb-2024 |
msaitoh |
Remove ryo@'s mail addresses.
|
Revision tags: netbsd-10-0-RC4 netbsd-10-0-RC3 netbsd-10-0-RC2 thorpej-ifq-base thorpej-altq-separation-base netbsd-10-0-RC1 netbsd-10-base bouyer-sunxi-drm-base
|
#
1.18 |
|
03-Aug-2022 |
ryo |
fix build with options PMAPBOOT_DEBUG and options DDB
|
Revision tags: thorpej-i2c-spi-conf2-base thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 cjep_staticlib_x-base thorpej-i2c-spi-conf-base
|
#
1.17 |
|
30-Apr-2021 |
skrll |
Make the ddb for pmap / pte information pmap agnostic
|
Revision tags: thorpej-cfargs-base thorpej-futex-base
|
#
1.16 |
|
20-Mar-2021 |
skrll |
branches: 1.16.2; Make pmapboot_enter panic if anything goes wrong and any mappings overlap rather than only doing it in locore.S
|
#
1.15 |
|
09-Jan-2021 |
jmcneill |
branches: 1.15.2; Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration.
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
branches: 1.10.2; KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.18 |
|
03-Aug-2022 |
ryo |
fix build with options PMAPBOOT_DEBUG and options DDB
|
Revision tags: thorpej-i2c-spi-conf2-base thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 cjep_staticlib_x-base thorpej-i2c-spi-conf-base
|
#
1.17 |
|
30-Apr-2021 |
skrll |
Make the ddb for pmap / pte information pmap agnostic
|
Revision tags: thorpej-cfargs-base thorpej-futex-base
|
#
1.16 |
|
20-Mar-2021 |
skrll |
branches: 1.16.2; Make pmapboot_enter panic if anything goes wrong and any mappings overlap rather than only doing it in locore.S
|
#
1.15 |
|
09-Jan-2021 |
jmcneill |
branches: 1.15.2; Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration.
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
branches: 1.10.2; KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.17 |
|
30-Apr-2021 |
skrll |
Make the ddb for pmap / pte information pmap agnostic
|
Revision tags: thorpej-i2c-spi-conf-base thorpej-cfargs-base thorpej-futex-base
|
#
1.16 |
|
20-Mar-2021 |
skrll |
Make pmapboot_enter panic if anything goes wrong and any mappings overlap rather than only doing it in locore.S
|
#
1.15 |
|
09-Jan-2021 |
jmcneill |
branches: 1.15.2; Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration.
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
branches: 1.10.2; KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.16 |
|
20-Mar-2021 |
skrll |
Make pmapboot_enter panic if anything goes wrong and any mappings overlap rather than only doing it in locore.S
|
Revision tags: thorpej-cfargs-base
|
#
1.15 |
|
09-Jan-2021 |
jmcneill |
Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration.
|
Revision tags: thorpej-futex-base
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
branches: 1.10.2; KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.15 |
|
09-Jan-2021 |
jmcneill |
Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration.
|
Revision tags: thorpej-futex-base
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
branches: 1.10.2; KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.14 |
|
11-Dec-2020 |
skrll |
s:aarch64/cpufunc.h:arm/cpufunc.h:
a baby step in the grand arm header unification challenge
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#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
Revision tags: thorpej-futex-base
|
#
1.10 |
|
17-Jul-2020 |
ryo |
KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.13 |
|
04-Dec-2020 |
skrll |
Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
Revision tags: thorpej-futex-base
|
#
1.10 |
|
17-Jul-2020 |
ryo |
KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.12 |
|
10-Nov-2020 |
skrll |
AA64 is not MIPS.
Change all KSEG references to directmap
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
Revision tags: thorpej-futex-base
|
#
1.10 |
|
17-Jul-2020 |
ryo |
KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
branches: 1.4.2; Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.11 |
|
07-Nov-2020 |
skrll |
Fix the use of the contiguous bit by checking the output address as well.
|
Revision tags: thorpej-futex-base
|
#
1.10 |
|
17-Jul-2020 |
ryo |
KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: netbsd-9-1-RELEASE ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.10 |
|
17-Jul-2020 |
ryo |
KNF. 80 cols, use tab.
|
#
1.9 |
|
17-Jul-2020 |
ryo |
Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter(). Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
|
#
1.8 |
|
16-Jul-2020 |
skrll |
pmapboot_enter simplication - bootpage_alloc in asm becomes pmapboot_pagealloc in C - PMAPBOOT_ENTER_NOBLOCK is removed as it's not used - PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on - physpage_allocator argument is removed as it's always pmapboot_pagealloc - Support for EARLYCONS without CONSADDR is removed so that the identity map for CONSADDR is always known.
For the assembly files: 2 files changed, 40 insertions(+), 89 deletions(-)
LGTM ryo
|
Revision tags: bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
branches: 1.6.4; Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.7 |
|
13-Apr-2020 |
maxv |
Add support for Branch Target Identification (BTI).
On the executable pages that have the GP (Guarded Page) bit, the semantic of the "br" and "blr" instructions is changed: the CPU expects the first instruction of the jump/call target to be "bti", and faults if it isn't.
We add the GP bit on the kernel .text pages (and incidentally the .rodata pages, but we don't care). The compiler adds a "bti c" instruction at the beginning of each C function. We modify the ENTRY() macros to manually add "bti c" in the asm functions.
cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j", which is bad because the functions begin with "bti c"; switch to "br x16", for the CPU to accept "bti c".
BTI helps defend against JOP/COP. Tested on Qemu.
|
Revision tags: phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406
|
#
1.6 |
|
29-Feb-2020 |
ryo |
Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
|
#
1.5 |
|
29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
|
Revision tags: ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
|
#
1.4 |
|
18-Jul-2019 |
skrll |
Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
|
Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
|
29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
#
1.6 |
|
29-Feb-2020 |
ryo |
Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions - pmap_extract() checks more strictly and consider the address tag
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1.5 |
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29-Feb-2020 |
ryo |
replace KSEG pages mapping code with generic function pmapboot_enter_range()
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Revision tags: ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base
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#
1.4 |
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18-Jul-2019 |
skrll |
Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
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Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
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1.3 |
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29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
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Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
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1.2 |
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05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
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1.1 |
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04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
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#
1.4 |
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18-Jul-2019 |
skrll |
Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and update the comments to be a little clearer.
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Revision tags: phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
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#
1.3 |
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29-Dec-2018 |
alnsn |
branches: 1.3.4; pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
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Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
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#
1.2 |
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05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
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#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|
Revision tags: isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118
|
#
1.3 |
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29-Dec-2018 |
alnsn |
pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.
|
Revision tags: pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020
|
#
1.2 |
|
05-Oct-2018 |
ryo |
branches: 1.2.2; fix build error without DDB
|
#
1.1 |
|
04-Oct-2018 |
ryo |
cleanup locore, and changed the way to map memories during boot. - add functions bootpage_enter() and bootpage_alloc() to adapt various layout of physical memory map. especially for 64bit physical memory layout. pmapboot_alloc() allocates pagetable pages from _end[]. - changed to map only the required amount for PA=VA identity mapping (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte). - changing page permission for kernel image, and making KSEG mapping are done at cpu_kernel_vm_init() instead of at locore. - optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.
reviewed by skrll@, thanks.
|