initial import of GMP 6.1.2. main changes from 5.1.3 below.

notes:
- support for thumb-less ARM chips was in our port of 5.1.3, but a
similar method has been provided upstream now
- someone should look at the AVX failure reports, and fix them

Changes between GMP version 6.1.0 and 6.1.1

FEATURES
* Work around faulty cpuid on some recent Intel chips (this allows GMP to run
on Skylake Pentiums).
* Support thumb-less ARM chips.

Changes between GMP version 6.0.* and 6.1.0

BUGS FIXED
* The public function mpn_com is now correctly declared in gmp.h.
* Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for
some obsolete CPUs.
* Various problems related to precision for mpf have been fixed.
* Fixed ABI incompatible stack alignment in calls from assembly code.
* Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI.
SPEEDUPS
* Speedup for Intel Broadwell and Skylake through assembly code making use of
new ADX instructions.
* Square root is now faster when the remainder is not needed. Also the speed
to compute the k-th root improved, for small sizes.
FEATURES
* New C++ functions gcd and lcm for mpz_class.
* New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap.
* New public mpq_cmp_z function, to efficiently compare rationals with
integers.
* Support for more 32-bit arm processors.
* Support for AVX-less modern x86 CPUs. (Such support might be missing either
because the CPU vendor chose to disable AVX, or because the running kernel
lacks AVX context switch support.)
* Support for NetBSD under Xen; we switch off AVX unconditionally under
NetBSD since a bug in NetBSD makes AVX fail under Xen.
MISC
* Tuned values for FFT multiplications are provided for larger number on
many platforms.

Changes between GMP version 5.1.* and 6.0.0
BUGS FIXED
* The function mpz_invert now considers any number invertible in Z/1Z.
* The mpn multiply code now handles operands of more than 2^31 limbs
correctly. (Note however that the mpz code is limited to 2^32 bits on
32-bit hosts and 2^37 bits on 64-bit hosts.)
SPEEDUPS
* Plain division of large operands is faster and more monotonous in operand
size.
* Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved
assembly.
* Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten
and vastly expanded assembly support. Speedup also for the older Core 2
and Nehalem.
* Faster mixed arithmetic between mpq_class and double.
FEATURES
* Support for new Intel and AMD CPUs.
* New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel
silent multiplication and squaring.
* New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing
side-channel silent division.
* New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent
conditional addition and subtraction.
* New public function mpn_sec_powm, implementing side-channel silent modexp.
* New public function mpn_sec_invert, implementing side-channel silent
modular inversion.
* Better support for applications which use the mpz_t type, but nevertheless
need to call some of the lower-level mpn functions. See the documentation
for mpz_limbs_read and related functions.