Remove memory barriers from the atomic_ops(3) atomic operations. They're
not needed for correctness.

Add the correct memory barriers to the gcc legacy __sync built-in
functions for atomic memory access. From the gcc documentation:

In most cases, these built-in functions are considered a full barrier.
That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.

type __sync_lock_test_and_set (type *ptr, type value, ...)

This built-in function is not a full barrier, but rather an acquire
barrier. This means that references after the operation cannot move to
(or be speculated to) before the operation, but previous memory stores
may not be globally visible yet, and previous memory loads may not yet
be satisfied.

void __sync_lock_release (type *ptr, ...)

This built-in function is not a full barrier, but rather a release
barrier. This means that all previous memory stores are globally
visible, and all previous memory loads have been satisfied, but
following memory reads are not prevented from being speculated to
before the barrier.

s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency. NFCI.

branches: 1.8.24;
Add aliases for the builtins used to implement C11/C++11 atomics.

branches: 1.7.2;
Try to hide the C runtime implementation specific __sync_* ops from librump,
to avoid duplicates.

Add support for the gcc __sync builtins.
Note that these need earmv6 or later to get the ldrex/strex instructions

Use foo{s} since it reduces the ifdefs for thumb

Make these under Thumb2

branches: 1.3.2;
Add dmb/dsb instructions as required by the armv7 arch man.

branches: 1.2.2; 1.2.4; 1.2.24;
Add assembly versions of atomic ops with ldrex/strex

branches: 1.1.2;
file atomic_or_32.S was initially added on branch thorpej-atomic.

s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency. NFCI.

branches: 1.8.24;
Add aliases for the builtins used to implement C11/C++11 atomics.

branches: 1.7.2;
Try to hide the C runtime implementation specific __sync_* ops from librump,
to avoid duplicates.

Add support for the gcc __sync builtins.
Note that these need earmv6 or later to get the ldrex/strex instructions

Use foo{s} since it reduces the ifdefs for thumb

Make these under Thumb2

branches: 1.3.2;
Add dmb/dsb instructions as required by the armv7 arch man.

branches: 1.2.2; 1.2.4; 1.2.24;
Add assembly versions of atomic ops with ldrex/strex

branches: 1.1.2;
file atomic_or_32.S was initially added on branch thorpej-atomic.

Add aliases for the builtins used to implement C11/C++11 atomics.

branches: 1.7.2;
Try to hide the C runtime implementation specific __sync_* ops from librump,
to avoid duplicates.

Add support for the gcc __sync builtins.
Note that these need earmv6 or later to get the ldrex/strex instructions

Use foo{s} since it reduces the ifdefs for thumb

Make these under Thumb2

branches: 1.3.2;
Add dmb/dsb instructions as required by the armv7 arch man.

branches: 1.2.2; 1.2.4; 1.2.24;
Add assembly versions of atomic ops with ldrex/strex

branches: 1.1.2;
file atomic_or_32.S was initially added on branch thorpej-atomic.

Don't use r4 (since it's caller saved). Use ip (it's available since we
are leaf functions).

Add armv6 variants of atomic ops which use ldrex/strex.
Add atomic_swap (all arm architectures) which uses swp and swpb.
Add membar_ops which uses armv6 data {sync, memory} barrier.
XXX let thorpej figure out the Makefile magic.

Pull atomic ops from HEAD.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")

sync with head

Sync with wrstuden-revivesa-base-2.

file atomic_or_32.S was added on branch wrstuden-revivesa on 2008-09-18 04:54:18 +0000

Rebase to HEAD as of a few days ago.

Rebase.