History log of /linux-master/sound/soc/intel/catpt/core.h
Revision Date Author Comments
# 85810c19 24-Nov-2020 Andy Shevchenko <andriy.shevchenko@linux.intel.com>

ASoC: Intel: catpt: Replace open coded variant of resource_intersection()

Since we have resource_intersection() helper, let's utilize it here.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>


# 3d324898 16-Nov-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Cleanup after power routines streamlining

With LPT switching to WPT-based power on/off routines, functions that
have been previously used by it are rendered redundant so remove them.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201116133332.8530-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# c440c724 16-Nov-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Streamline power routines across LPT and WPT

There is no need for separate power on/off routines for LPT and WPT as
as the protocol is shared for both platforms. Make WPT routines generic
and reuse them in LPT case too.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201116133332.8530-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# 8f80a834 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Simple sysfs attributes

Add sysfs entries for displaying version of FW currently in use as well
as dumping full FW information including build and log-providers hashes.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-10-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# a126750f 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: PCM operations

DSP designed for Lynxpoint and Wildcat Point offers no dynamic topology
i.e. all pipelines are already defined within firmware and host is
relegated to allocing stream for predefined pins. This is represented by
'catpt_topology' member.

Implementation covers all available pin types:
- system playback and capture
- two offload streams
- loopback (reference)
- bluetooth playback and capture

PCM DAI operations differentiate between those pins as some (mainly
offload) are to be handled differently - DSP expects wp updates on each
notify_position notification.

System playback has no volume control capability as it is routed to
mixer stream directly. Other primary streams - capture and two offloads
- offer individual volume controls.

Compared to sound/soc/intel/haswell this configures SSP device format
automatically on pcm creation.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-7-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# a9aa6fb3 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Firmware loading and context restore

For Lynxpoint and Wildcat Point solution, is it host's responsibility to
allocate SRAM regions and ensure those already taken are not overwritten
with other data until released. Blocks are transferred to SRAM - either
IRAM or DRAM - via DW DMA controller. Once basefw is booted, ownership
of DMA transfer is lost in favour of DSP.

Hosts reponsibilities don't end on initial block allocation and binary
transfer. During Dx transitions host must store FW runtime context from
DRAM before putting AudioDSP subsystem into lower power state. Said
context gets flashed after D0 entry to bring DSP right where it was just
before suspending.

Load and restore procedures are finalized with SRAM power gating and
adequate clock level selection. This power gates unused EBBs and clock
speed effectively reducing power consumption.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# ba202a7b 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Define DSP operations

Implement dsp lifecycle functions such as core RESET and STALL,
SRAM power control and LP clock selection. This also adds functions for
handling transport over DW DMA controller.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# 64b9b1b0 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Add IPC message handlers

Declare global and stream IPC message handlers for all known message
types.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# 92946c1d 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: catpt: Implement IPC protocol

Implement IRQ handlers for immediate and delayed replies and
notifications. Communication is synchronous and allows for serialization
of maximum one message at a time.

DSP may respond with ADSP_PENDING status for a request - known as
delayed reply - and when situation occurs, framework keeps the lock and
awaits upcoming response through IPCD channel which is handled in
bottom-half. Immediate replies spawn no BH at all as their processing is
very short.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-3-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>


# 4fac9b31 29-Sep-2020 Cezary Rojewski <cezary.rojewski@intel.com>

ASoC: Intel: Add catpt base members

Declare base structures, registers and extension routines for the catpt
solution.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>