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9ec1d748 |
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12-Dec-2023 |
David Heidelberg <david@ixit.cz> |
powerpc/fsl: Fix fsl,tmu-calibration to match the schema fsl,tmu-calibration is defined as a u32 matrix in Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml. Use matching property syntax. No functional changes. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20231212184515.82886-2-david@ixit.cz
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54877957 |
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31-Oct-2018 |
Scott Wood <oss@buserror.net> |
powerpc/fsl: Use new clockgen binding The driver retains compatibility with old device trees, but we don't want the old nodes lying around to be copied, or used as a reference (some of the mux options are incorrect), or even just being clutter. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> [scottwood: removed sysclk node added by Andy] Signed-off-by: Scott Wood <oss@buserror.net>
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ee73bcdb |
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04-Jan-2017 |
Hongtao Jia <hongtao.jia@nxp.com> |
powerpc/mpc85xx: Update TMU device tree node for T1023/T1024 Update #thermal-sensor-cells from 0 to 1 according to the new binding. The sensor specifier added is the monitoring site ID, and represents the "n" in TRITSRn and TRATSRn. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
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056f9657 |
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07-Dec-2016 |
Madalin Bucur <madalin.bucur@nxp.com> |
powerpc/fsl/dts: add QMan and BMan nodes on t1023 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
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d2d79dcc |
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15-Apr-2016 |
Chenhui Zhao <chenhui.zhao@nxp.com> |
powerpc/fsl: Fix rcpm compatible string For T1040, T1042, T1023, and T1024, they should use the compatible string "fsl,qoriq-rcpm-2.1". Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
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3045e409 |
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23-Nov-2015 |
Hongtao Jia <hongtao.jia@freescale.com> |
powerpc/mpc85xx: Add TMU device tree support for T1023/T1024 Also add nodes and properties for thermal management support. Meanwhile preprocessor support is needed using thermal of framework. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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da414bb9 |
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04-Aug-2015 |
Igal Liberman <Igal.Liberman@freescale.com> |
powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s) Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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2b6029e2 |
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09-Apr-2015 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/fsl-booke: Add T1024 QDS board support Add support for Freescale T1024/T1023 QorIQ Development System Board. T1024QDS is a high-performance computing evaluation, development and test platform for T1024 QorIQ Power Architecture processor. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [scottwood: vendor prefix: s/at24/atmel/ and trimmed detailed board description with too-long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
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ec66a97d |
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14-Apr-2015 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [scottwood@freescale.com: whitespace fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
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