#
7adc7b22 |
|
11-May-2021 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
powerpc/fsl: set fsl,i2c-erratum-a004447 flag for P2041 i2c controllers The i2c controllers on the P2040/P2041 have an erratum where the documented scheme for i2c bus recovery will not work (A-004447). A different mechanism is needed which is documented in the P2040 Chip Errata Rev Q (latest available at the time of writing). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Wolfram Sang <wsa@kernel.org>
|
#
54877957 |
|
31-Oct-2018 |
Scott Wood <oss@buserror.net> |
powerpc/fsl: Use new clockgen binding The driver retains compatibility with old device trees, but we don't want the old nodes lying around to be copied, or used as a reference (some of the mux options are incorrect), or even just being clutter. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> [scottwood: removed sysclk node added by Andy] Signed-off-by: Scott Wood <oss@buserror.net>
|
#
da414bb9 |
|
04-Aug-2015 |
Igal Liberman <Igal.Liberman@freescale.com> |
powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s) Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
7f6972a0 |
|
17-Apr-2015 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/mpc85xx: Add FSL QorIQ DPAA QMan support to device tree(s) Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Hai-Ying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> [Emil Medve: Sync with the upstream binding] Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> [Scott Wood: s/fsl,qman-channel-id/cell-index] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
|
#
d9fbe003 |
|
14-May-2015 |
Yangbo Lu <yangbo.lu@freescale.com> |
powerpc/dts: add eSDHC compatible list Add eSDHC compatible list for P2041/P3041/P4080/P5020/P5040. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
1e8ed06d |
|
27-Feb-2015 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s) Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Hai-Ying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> [Emil Medve: Sync with the upstream binding] Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
eaffcb0f |
|
06-Nov-2014 |
Emil Medve <Emilian.Medve@freescale.com> |
powerpc/dts: Factorize the clock control node Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1 Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
db75c22f |
|
04-Jun-2014 |
Valentin Longchamp <valentin.longchamp@keymile.com> |
powerpc/mpc85xx: fix fsl/p2041-post.dtsi clockgen mux2 The mux2 node is missing the clock-output-names field that is required by the clk-ppc-corenet driver. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
e83eb028 |
|
05-May-2014 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Diana Craciun <diana.craciun@freescale.com>
|
#
846c9443 |
|
07-May-2014 |
Diana Craciun <Diana.Craciun@freescale.com> |
powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips Updated the device trees according to the corenet-cf binding definition. Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
5d1a566e |
|
20-Jan-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
powerpc/mpc85xx: Update clock nodes in device tree The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
|
#
37f2808b |
|
05-Mar-2013 |
Stephen George <Stephen.George@freescale.com> |
powerpc/fsl-booke: Update DCSR EPU device tree entries for existing SoCs Identifies the epu as compatible with Chassis v1 Debug IP. Signed-off-by: Stephen George <Stephen.George@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
0408753f |
|
17-Jan-2013 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: describe the PAMU topology in the device tree The PAMU caches use the LIODNs to determine which cache lines hold the entries for the corresponding LIODs. The LIODNs must therefore be carefully assigned to avoid cache thrashing -- two active LIODs with LIODNs that put them in the same cache line. Currently, LIODNs are statically assigned by U-Boot, but this has limitations. LIODNs are assigned even for devices that may be disabled or unused by the kernel. Static assignments also do not allow for device drivers which may know which LIODs can be used simultaneously. In other words, we really should assign LIODNs dynamically in Linux. To do that, we need to describe the PAMU device and cache topologies in the device trees. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Stuart Yoder <stuart.yoder@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
465aceb8 |
|
17-Jan-2012 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add usb controller version info Add usb controller version info for the following: MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041, P3041, P3060, P5020 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
54986964 |
|
17-Nov-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Update SRIO device tree nodes Update all dts files that support SRIO controllers to match the new fsl,srio device tree binding. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
8b8673b8 |
|
07-Nov-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rework P2041RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|