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54877957 |
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31-Oct-2018 |
Scott Wood <oss@buserror.net> |
powerpc/fsl: Use new clockgen binding The driver retains compatibility with old device trees, but we don't want the old nodes lying around to be copied, or used as a reference (some of the mux options are incorrect), or even just being clutter. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> [scottwood: removed sysclk node added by Andy] Signed-off-by: Scott Wood <oss@buserror.net>
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ae9ac1d3 |
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10-Jun-2016 |
Sriram Dash <sriram.dash@freescale.com> |
powerpc/85xx: add aliases for usb nodes on t4240, b4860, and b4420 Add usb aliases for consistency with the other platforms. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
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da414bb9 |
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04-Aug-2015 |
Igal Liberman <Igal.Liberman@freescale.com> |
powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s) Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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52246445 |
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19-Sep-2015 |
poonam aggrwal <poonam.aggrwal@freescale.com> |
powerpc/b4860: Renamed the L2 caches To make provision for more than one L2 caches in the system, change the name from L2 to L2_1; same as in T4 platforms. * Also remove the L2 entry from common file "arch/powerpc/boot/dts/fsl/b4si-post.dtsi" Keep them only in separate files for b4860 and b4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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f2e7bfbb |
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05-May-2014 |
Diana Craciun <Diana.Craciun@freescale.com> |
powerpc/fsl: Updated device trees for platforms with corenet version 2 Updated the device trees according to the corenet-cf binding definition. Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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5d1a566e |
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20-Jan-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
powerpc/mpc85xx: Update clock nodes in device tree The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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4f6d45d7 |
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24-Oct-2013 |
Lijun Pan <LIJUN.PAN@FREESCALE.COM> |
powerpc/e6500: Include Power ISA properties b4420 and b4860 device trees do not have these properties. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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965fcb4d |
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04-Apr-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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