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b4337685 |
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25-Apr-2024 |
Manikanta Guntupalli <manikanta.guntupalli@amd.com> |
arm64: zynqmp: Add resets property for UART nodes Add resets property for UART0 and UART1 nodes Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Link: https://lore.kernel.org/r/20240425062358.1347684-3-manikanta.guntupalli@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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8b40a469 |
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17-Apr-2024 |
Rob Herring <robh@kernel.org> |
arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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237a1bbc |
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08-Jan-2024 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Align usb clock nodes with binding dwc3-xilinx.yaml defines 2 clocks which are not defined that's why define them (bus_early clock is moved to bus_clk in glue logic). With also describing kv260 assigned clock rates with assigned clocks. Also add missing status property to standard dwc3 core. Link: https://lore.kernel.org/r/aa4c65a8997c7a65f23da3a3088bb5eb64281307.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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672aa9ab |
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08-Jan-2024 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Comment all smmu entries SMMU is disabled by default and not all masters can be enabled at the same time because of limited number of entries. That's why comment all iommu properties but keep them for reference in DT. In XEN case they should be added back and Xen should have SMMU enabled by default. Also add IDs for DP and DPDMA. Link: https://lore.kernel.org/r/bdb012b1c86abb0d9aa88954196d886d1283e9b1.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
2385a6d8 |
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08-Jan-2024 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Introduce u-boot options node with bootscr-address Add u-boot options node with details about bootscr-address. c&p description from dtschema/schemas/options/u-boot.yaml: "Holds the full address of the boot script file. It helps in making automated flow easier by fetching the 64bit address directly from DT. Value should be automatically copied to the U-Boot 'scriptaddr' variable. When it is defined, bootscr-ram-offset property should be ignored. Actually only one of them should be present in the DT." Address is generic for all zynqmp boards because all of them have DDR starting from 0. Custom boards should revisit the location and aligned it based on their needs. Link: https://lore.kernel.org/r/4f5978d5a26fe0cd0cc6e54a97da1517bb925c01.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
34736222 |
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08-Jan-2024 |
Thippeswamy Havalige <thippeswamy.havalige@amd.com> |
arm64: zynqmp: Update ECAM size to discover up to 256 buses Update ECAM size to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Link: https://lore.kernel.org/r/4f7621a790f4aa35b3e7f74683d3ae4ffe820667.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
1993f676 |
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08-Jan-2024 |
Srinivas Neeli <srinivas.neeli@amd.com> |
arm64: zynqmp: Add resets property for CAN nodes Added resets property for CAN nodes. Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com> Link: https://lore.kernel.org/r/7bf0cc230f3c25010f9545f3f92f6f15a95d21ec.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
06d22ed6 |
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08-Jan-2024 |
Ilias Apalodimas <ilias.apalodimas@linaro.org> |
arm64: zynqmp: Add an OP-TEE node to the device tree Since the zynqmp boards can run upstream OP-TEE, and having the DT node present doesn't cause any side effects add it in case someone tries to load OP-TEE. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Link: https://lore.kernel.org/r/9ee7e8c263c453a8c9e6bc3b91fad78b0f54edc0.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
5710ea6a |
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21-Dec-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Rename zynqmp-power node to power-management Rename zynqmp-power node name to power-management which is more aligned with generic node name recommendation. Link: https://lore.kernel.org/r/bf24cde92c2b9e2824847687fab69fc25c533d53.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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a98b6987 |
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30-Nov-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Add missing destination mailbox compatible The commit 81186dc16101 ("dt-bindings: zynqmp: add destination mailbox compatible") make compatible string for child nodes mandatory that's why add it. Signed-off-by: Michal Simek <michal.simek@amd.com>
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eb2f7ff7 |
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18-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: xilinx: Remove address/size-cells from gem nodes Some boards are using one mdio bus which holds multiple phys and also boards are using mdio node for bus description. That's why there are cases where address/size-cells are unnecessary which is also reported by make W=1 dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle it based on used description. Error log: /axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/7252203d52af3ca8867764c8514affc4828e530d.1695040866.git.michal.simek@amd.com
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995d4ef0 |
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18-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: xilinx: Do not use '_' in DT node names Character '_' not recommended in node name. Use '-' instead. Pretty much run seds below for node names. s/zynqmp_ipi/zynqmp-ipi/ s/nvmem_firmware/nvmem-firmware/ s/soc_revision/soc-revision/ s/si5335_/si5335-/ Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5137958580c85a35cf6aadd1c33a2f6bcf81a9e5.1695040866.git.michal.simek@amd.com
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#
cf0e27cd |
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09-Jul-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Describe interrupts by using macros Use arm-gic.h and irq.h for interrupt description. It helps to improve readability of device tree file. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9d5bd17f37772be186cab17b06cc21351d36ff62.1688986332.git.michal.simek@amd.com
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#
04d54a0e |
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19-Jun-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Fix dwc3 usb interrupt description Based on DT binding dwc_usb3 is single entry without anything else. That's why combination dwc3_usb3, otg is not allowed. That's why split it to host and peripheral pair which both points to the same IRQ. DWC3 code is reading these two properties first before generic dwc_usb3. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6544d13afd9f3d8f5413e32684aa16e4d155e331.1687160244.git.michal.simek@amd.com
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#
3175b522 |
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08-Jun-2023 |
Varalaxmi Bingi <varalaxmi.bingi@amd.com> |
arm64: zynqmp: Setting default i2c clock frequency to 400kHz Setting default i2c clock frequency for ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3034ec006c8b11e025904d4cc2524255523636f6.1686227766.git.michal.simek@amd.com
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3011e0c8 |
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05-Jun-2023 |
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> |
arm64: zynqmp: Add L2 cache nodes Describe SoC L2 cache hierarchy. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com
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f1d48a12 |
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22-May-2023 |
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> |
arm64: zynqmp: Add pmu interrupt-affinity Based on dt-binding "This property should present when there is more than a single SPI" that's also case that's why explicitly specify interrupt affinity to avoid incorrect usage. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dde2e4b5ac6018adb9bfae05bb3800af6b7c0f0e.1684767562.git.michal.simek@amd.com
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4e4ddd3d |
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29-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Switch to amd.com emails Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
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5be4fbbf |
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02-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com
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#
3effc177 |
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02-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Sync node name address with reg (mailbox) Address in node name should match with the first reg property in DT. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5d8e80383912b8ff75409764efb75f3b85917087.1683034376.git.michal.simek@amd.com
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6ae507f0 |
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02-May-2023 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
arm64: zynqmp: Add resets property to sdhci nodes Add "resets" property to sdhci nodes. Resets property is used to reset the SD host controller when dynamic configuration support is enabled. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f8592d6454c024c8f8b92e56c9009c65ad1d54a.1683034376.git.michal.simek@amd.com
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9a18fb59 |
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02-May-2023 |
Michal Simek <michal.simek@amd.com> |
arm64: zynqmp: Rename ams_ps/pl node names Fix child node names to be aligned with commit 39dd2d1e251d ("dt-bindings: iio: adc: Add Xilinx AMS binding documentation") which requires names as ams-ps@ and ams-pl@. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/373136eccf8d22cdfb499adbc8d5f5510d6c1035.1683034376.git.michal.simek@amd.com
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a0bb549e |
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02-May-2023 |
Michal Simek <michal.simek@amd.com> |
Revert "arm64: dts: zynqmp: Add address-cells property to interrupt controllers" This reverts commit c6badbd2d321c19d4f55ee56b0ef12bb3352feac. Long time ago this was discussed with Rob at link below that there is no need to add address-cells to gpio and interrupt nodes that's why reverting this patch for ZynqMP. Also there is no visible DTC warning which was seen in past. Link: https://lore.kernel.org/r/91e3405245c89f134676449cf3822285798d2ed2.1612189652.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e3312910db0922bb8c24a8e681de41709ca11bdf.1683035456.git.michal.simek@amd.com
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37e78949 |
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21-Mar-2023 |
Parth Gajjar <parth.gajjar@amd.com> |
arm64: zynqmp: Add mali-400 gpu node for zynqmp Add mali-400 gpu node for zynqmp. Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar <parth.gajjar@amd.com> Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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b993ea2b |
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05-Jan-2023 |
Harini Katakam <harini.katakam@amd.com> |
arm64: dts: zynqmp: Add xlnx prefix to GEM compatible string cdns,zynq/zynqmp/versal-gem was recently deprecated in Linux in favour of xlnx prefix. Add this new compatible string and remove the existing cdns,zynqmp-gem compatible string. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/578a4fcbb4143888af954996a45f5e1110e0ee50.1672909426.git.michal.simek@amd.com
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185ffb48 |
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09-Dec-2022 |
Michal Simek <michal.simek@amd.com> |
arm64: dts: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi Remove clock-names from GEM nodes from clk-ccf because they should be only present in zynqmp.dtsi. And as is visible both clock-names defined didn't really match. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/24ce27f91a55ed04ca7ee2ff7db0c674702ef722.1670594284.git.michal.simek@amd.com
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53ba1b2b |
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09-Dec-2022 |
Piyush Mehta <piyush.mehta@xilinx.com> |
arm64: dts: zynqmp: Add mode-pin GPIO controller DT node Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0 controller. All Xilinx evaluation boards are using modepin gpio for ULPI reset that's why wire it directly in zynqmp instead of c&p the same line to every board specific file. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com
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32405e53 |
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23-Oct-2022 |
Michael Grzeschik <m.grzeschik@pengutronix.de> |
arm64: zynqmp: Enable hs termination flag for USB dwc3 controller Since we need to support legacy phys with the dwc3 controller, we enable this quirk on the zynqmp platforms. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Link: https://lore.kernel.org/r/20221023215649.221726-1-m.grzeschik@pengutronix.de Signed-off-by: Michal Simek <michal.simek@amd.com>
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56f2b1ff |
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30-Nov-2022 |
Michal Simek <michal.simek@amd.com> |
arm64: xilinx: Fix opp-table-cpu OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. The same change was done by commit c6d4a8977598 ("ARM: tegra: Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a ("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3297772b58953e4afd91f7a4bd845713e36e1e27.1652713489.git.michal.simek@amd.com
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400f6af0 |
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14-Nov-2022 |
Tanmay Shah <tanmay.shah@amd.com> |
arm64: dts: xilinx: zynqmp: Add RPU subsystem device node RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains. Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221114233940.2096237-3-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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1f367ee9 |
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06-Aug-2021 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
arm64: dts: zynqmp: Add ports for the DisplayPort subsystem The DPSUB DT bindings now specify ports to model the connections with the programmable logic and the DisplayPort output. Add them to the device tree. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@amd.com>
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271c1fa0 |
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19-Jan-2022 |
Robert Hancock <robert.hancock@calian.com> |
arm64: dts: zynqmp: add AMS driver to device tree Add an entry to the ZynqMP device tree to support the AMS device which now has a driver in mainline. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220120010246.3794962-2-robert.hancock@calian.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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d8b1c3d0 |
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27-Jan-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: dts: zynqmp: Move USB clocks to dwc3 node These clocks are not used by the dwc3-xilinx driver except to enable/disable them. Move them to the dwc3 node so its driver can use them to configure the reference clock period. Tested-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Robert Hancock <robert.hancock@calian.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20220127200636.1456175-7-sean.anderson@seco.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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e461bd6f |
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27-Jan-2022 |
Robert Hancock <robert.hancock@calian.com> |
arm64: dts: zynqmp: Added GEM reset definitions The Cadence GEM/MACB driver now utilizes the platform-level reset on the ZynqMP platform. Add reset definitions to the ZynqMP platform device tree to allow this to be used. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3a14f0e6 |
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12-Jan-2022 |
Michael Tretter <m.tretter@pengutronix.de> |
arm64: zynqmp: Rename dma to dma-controller The ZynqMP dma engines are actually dma-controllers as specified by the device tree binding. Rename the device tree nodes accordingly. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220112151541.1328732-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1ff2d58e |
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12-Jan-2022 |
Michael Tretter <m.tretter@pengutronix.de> |
arm64: zynqmp: Add missing #dma-cells property Requesting the dma controllers fails if #dma-cells is not defined. Add the missing property. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220112151541.1328732-3-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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eceb6f86 |
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08-Dec-2021 |
David Heidelberg <david@ixit.cz> |
arm64: xilinx: dts: drop legacy property #stream-id-cells Property #stream-id-cells is legacy leftover and isn't currently documented nor used. Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20211208184846.101166-1-david@ixit.cz Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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b61c4ff9 |
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05-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards The commit 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") finally add proper support for Xilinx dwc3 driver. This patch is adding DT description for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
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812fa2f0 |
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06-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Fix serial compatible string Based on commit 65a2c14d4f00 ("dt-bindings: serial: convert Cadence UART bindings to YAML") compatible string should look like differently that's why fix it to be aligned with dt binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/89b36e0a6187cc6b05b27a035efdf79173bd4486.1628240307.git.michal.simek@xilinx.com
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bc97eb86 |
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14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add reset description for sata Sata needs to get reset before configuration that's why add property for it there. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/b7f61daa2fe1a2300767af73c46b8082088f741a.1623684253.git.michal.simek@xilinx.com
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a787716a |
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14-Jun-2021 |
Srinivas Neeli <srinivas.neeli@xilinx.com> |
arm64: zynqmp: Update rtc calibration value As per the design specification "The 16-bit Seconds Calibration Value represents the number of Oscillator Ticks that are required to measure the largest time period that is less than or equal to 1 second. For an oscillator that is 32.768 KHz, this value will be 0x7FFF." Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0d36d9fe999ff82f10d42ab5fc0d1e907c26ac34.1623684253.git.michal.simek@xilinx.com
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69aa2de1 |
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14-Jun-2021 |
Mounika Grace Akula <mounika.grace.akula@xilinx.com> |
arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value This patch adds reset-on-timeout to FPD WDT which will trigger an interrupt to PMU when watchdog expiry happens and PMU takes the necessary action. If this property is not enabled, reason will not be known when watchdog expiry happens. This patch also modifies the default timeout to 60 seconds. Reason is that if u-boot enables WDT, it will set the timeout to 10 seconds and this is not enough to boot till Linux and start the WDT application in Linux. 60 seconds is the maximum safest value to boot till Linux and start the WDT application. Users need to change this timeout value to fit their needs. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5848a81447921240fddfe2f5749ae0746fcbbdbd.1623684253.git.michal.simek@xilinx.com
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da2618b5 |
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14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi Using clock firmware driver is not the only one option how to configure clock. In past fixed clocks were also used and that configuration is still valid that's why move clock firmware node to the same file where zynqmp_clk references are used. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/48bfd8cf0de4d10b9c4d745218595f28954f70d5.1623684253.git.michal.simek@xilinx.com
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d58f9227 |
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14-Jun-2021 |
Stefano Stabellini <stefano.stabellini@xilinx.com> |
arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi The SMMU is disabled in device tree so this change has no impact. The benefit is that this way it is in sync with xen.dtsi. Xen enables the SMMU and makes use of it. Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/43f21f5033f7806fba049474bced6131c8cb98ba.1623684253.git.michal.simek@xilinx.com
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c821045f |
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14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add pinctrl description for all boards The commit 1dccb5ec0123 ("dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver") and commit 8b242ca700f8 ("pinctrl: Add Xilinx ZynqMP pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver that's why describe pins configuration for current boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
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4234645d |
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14-Jun-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Disable CCI by default There is no reason to have CCI no enabled by default. Enable it when your system configuration requires it. In Xilinx configuration flow this is work for Device Tree Generator which reads information from HW Design configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f507d45fbaa0bd31f641e758efa40a2532466ced.1623684253.git.michal.simek@xilinx.com
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b06112cd |
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06-Mar-2021 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
arm64: dts: zynqmp: Add power domain for the DisplayPort DMA controller The DisplayPort DMA controller (DPDMA) is located in the same power domain as the DisplayPort Subsystem (DPSUB). Specify the power domain in the device tree. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210306230915.14979-1-laurent.pinchart@ideasonboard.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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b0f89cf5 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add DisplayPort subsystem Add a DT node for the DisplayPort subsystem, a hard IP present in the Zynq Ultrascale+ MPSoC. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com
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7b6714b3 |
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21-Jan-2021 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
arm64: dts: zynqmp: Add DPDMA node Add a DT node for the DisplayPort DMA engine (DPDMA). Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3d11015512a085592f2aca76eeddc04178d38bbe.1611232558.git.michal.simek@xilinx.com
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8ac47837 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add missing iommu IDs Add missing iommu IDs to all IPs which have IDs assigned. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/78afdafdc60c3182318894f2808f7f337a798278.1611224800.git.michal.simek@xilinx.com
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1f9fcf65 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add missing lpd watchdog node Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain) watchdogs. There are cases where also LPD WDT should be used by Arm cores that's why list it with disabled status. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0489a1d5528614f1d570ea153d38b813f0c1eb9f.1611224800.git.michal.simek@xilinx.com
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cbf8bed0 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Wire zynqmp qspi controller Add missing ZynqMP qspi IP. It works in single mode only. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com
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41b452a5 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Wire arasan nand controller Add missing arasan controller with clocks. Disable it by default. Every board can enable it with specifying others properties. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/05cc1ce7973ac5200aeca428c137b422c827c5e8.1611224800.git.michal.simek@xilinx.com
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002002c0 |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add label for zynqmp_ipi Add label which is used by bootloader for adding bootloader specific flag. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
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42cb66dc |
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21-Jan-2021 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Enable reset controller driver Enable reset controller to be prepared for use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4fb62952f61e5046d750fff0e3e469c7abd1d0d0.1611224800.git.michal.simek@xilinx.com Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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c6badbd2 |
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02-Dec-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add address-cells property to interrupt controllers The commit 3eb619b2f7d8 ("scripts/dtc: Update to upstream version v1.6.0-11-g9d7888cbf19c") updated dtc version which also contained DTC commit "81e0919a3e21 checks: Add interrupt provider test" where reasons for this checking are mentioned as "A missing #address-cells property is less critical, but creates ambiguities when used in interrupt-map properties, so warn about this as well now." That's why add address-cells property to gic and gpio nodes to get rid of this warning. CC: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/e4f54ddce33b79a783aa7c76e0dc6e9787933610.1606918493.git.michal.simek@xilinx.com
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9854bc7d |
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12-Nov-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Wire mailbox with zynqmp-power driver The support to driver was added by commit ffdbae28d9d1 ("drivers: soc: xilinx: Use mailbox IPI callback") that's why also enable it via DT by default. It setups communication with firmware via IPI interface. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5d3523150890e494df308ee69523d0f0e7b33b22.1605185549.git.michal.simek@xilinx.com
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48ab2996 |
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29-Sep-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Fix pcie ranges description DT schema is checking tuples which should be properly separated. The patch is doing this separation to avoid the following warning: ..yaml: axi: pcie@fd0e0000:ranges: [[33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0]] is not valid under any of the given schemas (Possible causes of the failure): ...dt.yaml: axi: pcie@fd0e0000:ranges: True was expected ...dt.yaml: axi: pcie@fd0e0000:ranges:0: [33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0] is too long Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com
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74790cf9 |
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10-Nov-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Move gic node to axi bus The reason for this change is that after change from amba to axi U-Boot started to show error like: Unable to update property /axi/ethernet@ff0e0000:mac-address, err=FDT_ERR_NOTFOUND Unable to update property /axi/ethernet@ff0e0000:local-mac-address, err=FDT_ERR_NOTFOUND The reason is implementation in fdt_nodename_eq_() which is taken from dtc to the kernel and to the U-Boot. Especially DTC commit d2a9da045897 ("libfdt: Make unit address optional for finding nodes") which is in DTC from 2007. The part of commit description is " This is contrary to traditional OF-like finddevice() behaviour, which allows the unit address to be omitted (which is useful when the device name is unambiguous without the address)." The kernel commit dfff9066e60e ("arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml") changed amba-apu/amba to axi@0/axi but fdt_nodename_eq_() detects /axi/ as match for /axi@0/ because of commit above. That's why it easier to fix one DT inside the kernel by moving GIC node from own bus to generic axi bus as is done by others SoCs. This will avoid incorrect match because the unit address is omitted. Reported-by: Paul Thomas <pthomas8589@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com
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db7691f9 |
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24-Aug-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Remove undocumented u-boot properties u-boot, DT properties are not documented anywhere in Linux DT binding that's why remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8ba339425b9c9f319bdedce7741367055a30713c.1598257720.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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35292518 |
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24-Aug-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Remove additional compatible string for i2c IPs DT binding permits only one compatible string which was decribed in past by commit 63cab195bf49 ("i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC"). The commit aea37006e183 ("dt-bindings: i2c: cadence: Migrate i2c-cadence documentation to YAML") has converted binding to yaml and the following issues is reported: ...: i2c@ff030000: compatible: Additional items are not allowed ('cdns,i2c-r1p10' was unexpected) From schema: .../Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml fds ...: i2c@ff030000: compatible: ['cdns,i2c-r1p14', 'cdns,i2c-r1p10'] is too long The commit c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string") has added the second compatible string but without removing origin one. The patch is only keeping one compatible string "cdns,i2c-r1p14". Fixes: c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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dfff9066 |
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23-Aug-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml Rename amba-apu and amba to AXI. Based on Xilinx ZynqMP TRM (Chapter 15) chip is "using the advanced eXtensible interface (AXI) point-to-point channels for communicating addresses, data, and response transactions between master and slave clients." Issues are reported as: ...: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml ...: amba-apu@0: $nodename:0: 'amba-apu@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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8d53ecfb |
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29-Jun-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: xilinx: Align IOMMU nodename with dtschema Fix dtschema validator warnings like: smmu@fd800000: $nodename:0: 'smmu@fd800000' does not match '^iommu@[0-9a-f]*' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org
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b4b6fb8d |
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29-Jun-2020 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
arm64: dts: zynqmp: Add GTR transceivers Add a DT node for the PS-GTR transceivers. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20200629120054.29338-4-laurent.pinchart@ideasonboard.com
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81822732 |
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25-Feb-2020 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Fix GIC compatible property dtbs_check is showing warning around GIC compatible property as interrupt-controller@f9010000: compatible: ['arm,gic-400', 'arm,cortex-a15-gic'] is not valid under any of the given schemas Similar change has been done also by commit 5400cdc1410b ("ARM: dts: sunxi: Fix GIC compatible") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a50412fbb520954e4602f274f19a7ffbd1154ead.1582621224.git.michal.simek@xilinx.com
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88affa2f |
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17-Feb-2020 |
Kalyani Akula <kalyani.akula@xilinx.com> |
arm64: zynqmp: Add Xilinx AES node This patch adds a AES DT node for Xilinx ZynqMP SoC. Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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959b86ae |
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07-Nov-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
arm64: dts: xilinx: Add the power nodes for zynqmp Add power domain nodes for zynqmp. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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9c8a47b4 |
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07-Nov-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
arm64: dts: xilinx: Add the clock nodes for zynqmp Add clock nodes for zynqmp based on CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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a8fdb80f |
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21-Nov-2019 |
Manish Narani <manish.narani@xilinx.com> |
arm64: zynqmp: Add ZynqMP SDHCI compatible string Add the new compatible string for ZynqMP SD Host Controller for its use in the Arasan SDHCI driver for some of the ZynqMP specific operations. Add required properties for the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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b7178639 |
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18-Oct-2019 |
Nava kishore Manne <nava.manne@xilinx.com> |
arm64: zynqmp: Add support for zynqmp nvmem firmware driver Add support for zynqmp nvmem firmware driver. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> [m.tretter@pengutronix.de: move to subnode of firmware] Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
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c40d1cce |
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18-Oct-2019 |
Nava kishore Manne <nava.manne@xilinx.com> |
arm64: zynqmp: Label whole PL part as fpga_full region This will simplify dt overlay structure for the whole PL. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
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9c363392 |
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18-Oct-2019 |
Nava kishore Manne <nava.manne@xilinx.com> |
arm64: zynqmp: Add support for zynqmp fpga manager Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> [m.tretter@pengutronix.de: moved to subnode of firmware] Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
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ef0d933e |
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18-Oct-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
arm64: zynqmp: Add firmware DT node Add firmware DT node in ZynqMP device tree. This node uses bindings as per new firmware interface driver. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
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31af04cd |
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14-Jan-2019 |
Rob Herring <robh@kernel.org> |
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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d1d4445a |
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08-Nov-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Fix node names which contain "_" s/_/-/ for node names. It fixes warnings like this: ... Warning (node_name_chars_strict): /cpu_opp_table: Character '_' not recommended in node name ... Issues reported by make dtbs W=12 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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4556b160 |
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08-Nov-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Add missing gpio-controller to ps gpio Add missing gpio-controller property to ps gpio. This was found via DT schema validation. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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e7abd894 |
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25-Oct-2018 |
Manish Narani <manish.narani@xilinx.com> |
arm64: dts: zynqmp: Add DDRC node Add ddrc memory controller node in dts. The size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at 0xFD090208 from this driver. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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9fd609ff |
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26-Sep-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: dts: zynqmp: Use mmc@ instead sdhci@ mmc name is recommended based on devicetree specification. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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e9880240 |
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23-Aug-2018 |
Amit Kucheria <amit.kucheria@linaro.org> |
arm64: dts: Fix various entry-method properties to reflect documentation The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Fix the cpu-capacity.txt documentation that uses the incorrect value so we don't get copy-paste errors like these. Clarify the language in idle-states.txt by removing the reference to the psci bindings that might be causing this confusion. Finally, fix devicetrees of various boards to reflect current documentation. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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b9c74682 |
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17-Jan-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add SPDX license identifier Add SPDX identifier as was done by for example by: "License cleanup: add SPDX GPL-2.0 license identifier to files with no license" (commit <b24413180f5600bcb3bb70fbed5cf186b60864bd>) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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0f780ca0 |
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17-Jan-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Fix alignment in dts files Trivial changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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33af509f |
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17-Jan-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Use zynqmp specific compatible string for macb The patch "devicetree: Add compatible string for Zynq Ultrascale+ MPSoC" (commit <988d6f07fc0a29e392035ba56e3bcfaf7b397d95>) introduced specific compatible string for ZynqMP which should be used first. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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932bd0d8 |
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09-Oct-2015 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add fpd/lpd dmas Wire fpd and lpd dma channels to zynqmp.dtsi. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2f9ed199 |
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09-Mar-2017 |
Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> |
arm64: zynqmp: Set status disabled in dtsi Do not enable smmu via dtsi. Enable it in board file when needed. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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27af3993 |
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27-Nov-2015 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add new uartps compatible string Mainline kernel has r1p12 compatible string now. Use this new compatible string and also append generic compatible string. Keep in your mind that using this generic compatible string not all uart features will be available. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org>
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e199f2cc |
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26-Nov-2015 |
Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
arm64: zynqmp: Correct IRQ nr for the SMMU Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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7fb7820c |
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09-Oct-2015 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add support for RTC Add support for RTC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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4a6514d5 |
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02-Aug-2016 |
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
arm64: zynqmp: Adding prefetchable memory space to pcie node Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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8c50b1e4 |
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26-Nov-2015 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add CCI-400 node Add CCI-400 node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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17e76f95 |
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14-Sep-2016 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add dcc console for zynqmp Add debug console to dtsi to be able to enable it in board dts file. Keep in your mind that every core has separate dcc port in case you want to run SMP kernel. DCC is very helpful communication channel for debugging. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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e31b7bb8 |
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05-Feb-2017 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
arm64: zynqmp: Add operating points Adding operating-points-v2 for zynqmp. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1e4e25c8 |
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20-Oct-2016 |
Stefan Krsmanovic <stefan.krsmanovic@aggios.com> |
arm64: zynqmp: Add idle state for ZynqMP Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0 idle state is added in this patch. References to the idle-states node are added in all CPU nodes. Time values: entry/exit latencies and min-residency, needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0 and Extended StateID format. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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400e188f |
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06-Feb-2017 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Add references to cpu nodes Add missing references to all cpu nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org>
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d15c56ca |
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21-Mar-2017 |
Rob Herring <robh@kernel.org> |
arm64: dts: xilinx: fix PCI bus dtc warnings dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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c415f9e8 |
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22-Dec-2016 |
Moritz Fischer <mdf@kernel.org> |
ARM64: zynqmp: Fix i2c node's compatible string The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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4ea2a6be |
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15-Nov-2016 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Fix W=1 dtc 1.4 warnings The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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f2a89d3b |
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01-Aug-2016 |
Marc Zyngier <maz@kernel.org> |
arm64: dts: Fix broken architected timer interrupt trigger The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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908c9e73 |
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03-Nov-2015 |
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com> |
ARM64: zynqmp: Correct the watchdog timer interrupt number Corrected the watchdog timer interrupt number. Origin value was for CSUPMU watchdog. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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886e7ddd |
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02-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Add missing interrupt-parent to PMU node ZynqMP is not using global interrupt-parent setting that's why it has to be listed in every node separately. PMU node missed it and this patch is adding it. Reported-by: John Linn <John.Linn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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78b83b8c |
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09-Aug-2016 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Add PCIe node Add PCIe node with prefetchable memory which goes beyond 4GB. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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7393fd86 |
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11-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Use 64bit size cell format Use 64bit size cell format instead of 32bit for memory description. Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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e753dc03 |
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12-May-2016 |
Alexander Graf <agraf@suse.de> |
ARM64: zynqmp: Align gic ranges for 64k in device tree The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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5087bccb |
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20-Oct-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Extract clock information from EP108 Extract clocks and put it specific file to help with platform autogeneration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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72e5df43 |
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11-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Keep gpio node alphabetically sorted No functional change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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bdd57390 |
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23-Oct-2015 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
ARM64: zynqmp: DT: Add interrupt-controller property to GPIO GPIO can be used as interrupt-controller. Add the missing properties to the GPIO node. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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f49310dc |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Move SPI nodes to the right location Keep nodes sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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8fd7a775 |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Move uart and ttcs to the right location Sort nodes in DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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22eda14a |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Add DWC3 usb support Add usb nodes to DTSI and enable both of them on ep108. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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ff92e361 |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Add SMMU support Add SMMU DT node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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3a8691f5 |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Add CANs node for platform Also enable can0 for ep108. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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b72b44b6 |
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27-Jul-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: zynqmp: Use zynqmp specific compatible string for gpio The patch: "gpio: Added support to Zynq Ultrascale+ MPSoC" (sha1: bdf7a4ae371894b4dc10b5820006b0a82d484929) added zynqmp specific features. This patch is switching the driver to use the zynqmp compatible string. Also enable the driver for ep108 platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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8fae442f |
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10-Jun-2015 |
Suneel Garapati <suneel.garapati@xilinx.com> |
devicetree: xilinx: zynqmp: add sata node add sata node with sata fixed clock nodes in dtsi file. enable sata in zynqmp-ep108.dts with broken-gen2. Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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5d1b79d2 |
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09-Mar-2015 |
Michal Simek <michal.simek@xilinx.com> |
ARM64: Add new Xilinx ZynqMP SoC Initial version of device tree for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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