#
491821ce |
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15-Feb-2024 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-7-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
62b19a64 |
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23-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Convert usb_serdes_mux node into reg-mux This removes a dependency on the parent node being a syscon node. Convert from mmio-mux to reg-mux adjusting node name and properties as needed. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124184722.150615-6-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
4cd6d56c |
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23-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Convert serdes_ln_ctrl node into reg-mux This removes a dependency on the parent node being a syscon node. Convert from mmio-mux to reg-mux adjusting node name and properties as needed. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124184722.150615-5-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
111f6dac |
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22-Jan-2024 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e: Add MIT license along with GPL-2.0 Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de> Cc: Jerome Neanne <jneanne@baylibre.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
1b62a3cf |
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13-Dec-2023 |
Manorit Chawdhry <m-chawdhry@ti.com> |
arm64: dts: ti: k3-j7*: Add additional regs for DMA components Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
6507bfa7 |
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05-Oct-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-*: Convert NAVSS to simple-bus "simple-mfd" as standalone compatible is frowned upon, so model main and MCU NAVSS (Navigator SubSystem) nodes as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-3-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
00ae4c39 |
|
09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board level C6x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C6x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Tested-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230809180145.53158-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
35dba715 |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board level C7x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C7x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Tested-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230809180145.53158-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
8757108b |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-9-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
6fbd1310 |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
702110c2 |
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09-Aug-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3: Add cfg reg region to ringacc node Add register range of ringacc cfg node to all k3 SoC dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
8d08d7aa |
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21-Jul-2023 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: Use local header for SERDES MUX idle-state values The DTS uses constants for SERDES MUX idle state values which were earlier provided as bindings header. But they are unsuitable for bindings. So move these constants in a header next to DTS. Also add J784S4 SERDES4 lane definitions which were missed earlier. Suggested-by: Nishanth Menon <nm@ti.com> Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/ Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Roger Quadros <rogerq@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
2a7cc7be |
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13-Jul-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclk TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a syscon compatibility. Fixes the following dtbs_check warnings: compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
48a498a2 |
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05-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: add missing space before { Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon <nm@ti.com>
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#
414772b8 |
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02-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon <nm@ti.com>
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#
19bfd518 |
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04-May-2023 |
Neha Malcom Francis <n-francis@ti.com> |
arm64: dts: ti: k3-j721e: Add ESM support Add address entry mapping ESM on J721E. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
72a44d1c |
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31-May-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in Technical Reference Manual[1] under "Timer IO Muxing Control Registers" and "Timer IO Muxing Control Registers", and the "Timers Overview" chapters. We do not expose the cascade_en bit due to the racy usage of independent 32 bit registers in-line with the timer instantiation in the device tree. The MCU timer controls are also marked as reserved for usage by the MCU firmware. [1] http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
7f209dd1 |
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31-May-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e: Add general purpose timers There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. These instantiation differs from J7200 and other SoCs with the device IDs and clocks involved for muxing. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
b0efb45d |
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14-May-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
731c6ded |
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14-May-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
a0cfd88d |
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14-May-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
af398252 |
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24-Apr-2023 |
Bhavya Kapoor <b-kapoor@ti.com> |
arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
76aa309f |
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21-Mar-2023 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-j721e: Add MCSPI nodes J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
a2ff7f11 |
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15-Mar-2023 |
Siddharth Vadapalli <s-vadapalli@ti.com> |
arm64: dts: ti: k3-j721e: Add CPSW9G nodes TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
4f4b30a7 |
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03-Feb-2023 |
Bhavya Kapoor <b-kapoor@ti.com> |
arm64: dts: ti: k3-j721e-main: Remove ti,strobe-sel property According to latest errata of J721e [1], (i2024) 'MMCSD: Peripherals Do Not Support HS400' which applies to MMCSD0 subsystem. Speed modes supported has been already updated but missed dropping 'ti,strobe-sel' property which is only required by HS400 speed mode. Thus, drop 'ti,strobe-sel' property from kernel dtsi for J721e SoC. [1] https://www.ti.com/lit/er/sprz455/sprz455.pdf Fixes: eb8f6194e807 ("arm64: dts: ti: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems") Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Diwakar Dhyani <d-dhyani@ti.com> Reviewed-by: Nitin Yadav <n-yadav@ti.com> Link: https://lore.kernel.org/r/20230203073724.29529-1-b-kapoor@ti.com
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#
a315097a |
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07-Nov-2022 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: k3-j721e-main: Drop RNG clock The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-3-j-choudhary@ti.com
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#
26c50124 |
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31-Oct-2022 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: k3-j721e-main: Drop dma-coherent in crypto node crypto driver itself is not dma-coherent. So drop it. Fixes: 8ebcaaae8017 ("arm64: dts: ti: k3-j721e-main: Add crypto accelerator node") Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20221031152520.355653-3-j-choudhary@ti.com
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#
20f67d1d |
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06-Nov-2022 |
Vijay Pothukuchi <vijayp@ti.com> |
arm64: dts: ti: k3-j721e-main: Add dts nodes for EHRPWMs Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Includes a minor formatting fixup for the serdes node to line up the nodes appropriately. Signed-off-by: Vijay Pothukuchi <vijayp@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107070009.11500-2-r-ravikumar@ti.com
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#
7e48b665 |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-9-afd@ti.com
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#
39e7758b |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable MCAN nodes at the board level MCAN nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-5-afd@ti.com
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#
256596ad |
|
20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable MCASP nodes at the board level MCASP nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCASP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-4-afd@ti.com
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#
282c4ad3 |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable I2C nodes at the board level I2C nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-3-afd@ti.com
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#
fe17e20f |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j721e: Enable UART nodes at the board level UART nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-2-afd@ti.com
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f42f6f9e |
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08-Aug-2022 |
Daniel Parks <danielrparks@ti.com> |
arm64: dts: ti: k3-j721e-main: fix RNG node clock id The RNG node for this platform claims pka_in_clk. Change it to claim the correct clock x1_clk. [1] [1]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721e/clocks.html#clocks-for-sa2-ul0-device Signed-off-by: Daniel Parks <danielrparks@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/f29e2c65dc7310a926af8a676651592afac04b03.1659981162.git.danielrparks@ti.com
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92c996f4 |
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29-Apr-2022 |
Tomi Valkeinen <tomi.valkeinen@ti.com> |
arm64: dts: ti: k3-j721e-*: add DP & DP PHY Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add the required phy link nodes in the board dts files. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com
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a06ed27f |
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15-Feb-2022 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org # 5.10+ Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com
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4688a4fc |
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22-Nov-2021 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j721e: Add support for MCAN nodes Add support for 14 MCAN controllers in main domain and 2 MCAN controllers present in mcu domain. All the MCAN controllers support classic CAN messages as well as CAN_FD messages. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com
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3f92a5be |
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26-Nov-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node Fix 'dtbs_check' in serdes_ln_ctrl (mux@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211126084555.17797-3-kishon@ti.com
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5f466335 |
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14-Sep-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Fix "bus-range" upto 256 bus number for PCIe commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") restricted PCIe bus numbers from 0 to 15 (due to SMMU restriction in J721E). However since SMMU is not enabled, allow the full supported bus numbers from 0 to 255. Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210915055358.19997-3-kishon@ti.com
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9af3ef95 |
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14-Sep-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Fix "max-virtual-functions" in PCIe EP nodes commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") added "max-virtual-functions" to have 16 bit values. Fix "max-virtual-functions" in PCIe endpoint (EP) nodes to have 8 bit values instead of 16. Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210915055358.19997-2-kishon@ti.com
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d65f069e |
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07-Jun-2021 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes 8250_omap compatible UART IPs on all SoCs have registers aligned at 4 byte address boundary and constant byte addressability. Thus there is no need for reg-io-width or reg-shift DT properties. These properties are not used by 8250_omap driver nor documented as part of binding document. Therefore drop them. This is in preparation to move omap-serial.txt to YAML format. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
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2427bfb3 |
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03-Jun-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node Add #clock-cells property to serdes DT node since the serdes is also now modeled as a clock provider and include the input clocks "pll0_refclk" and "pll1_refclk" which are parents to the clocks modeled by serdes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210603143427.28735-3-kishon@ti.com
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5c6d0b55 |
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03-Jun-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Rename the external refclk inputs to the SERDES from dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1 respectively. Also move the external refclk DT nodes outside the cbass_main DT node. Since in j721e common processor board, only the cmn_refclk1 is connected to 100MHz clock, fix the clock frequency. Fixes: afd094ebe69f ("arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210603143427.28735-2-kishon@ti.com
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7ce11d47 |
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01-Jun-2021 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add ICSSG MDIO nodes The ICSSGs on K3 J721E SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each ICSSG instance. The MDIO module used within the ICSSG is similar to the MDIO Controller used in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the MDIO operations. The nodes are added and enabled in the common k3-j721e-main.dtsi file by default, and disabled in the existing J721E board dts file. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210601150032.11432-3-s-anna@ti.com
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cab12bad |
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11-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3*: Introduce reg definition for interrupt routers Interrupt routers are memory mapped peripherals, that are organized in our dts bus hierarchy to closely represents the actual hardware behavior. However, without explicitly calling out the reg property, using 2021.03+ dt-schema package, this exposes the following problem with dtbs_check: /arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: interrupt-controller0: {'type': 'object'} is not allowed for {'compatible': ['ti,sci-intr'], ..... Even though we don't use interrupt router directly via memory mapped registers and have to use it via the system controller, the hardware block is memory mapped, so describe the base address in device tree. This is a valid, comprehensive description of hardware and permitted by the existing ti,sci-intr schema. Reviewed-by: Tero Kristo <kristo@kernel.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210511194821.13919-1-nm@ti.com
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9ecdb6d6 |
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10-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator subsystem via explicit ranges Instead of using empty ranges property, lets map explicitly the address range that is mapped onto the dma / navigator subsystems (navss/dmss). This is also exposed via the dtbs_check with dt-schema newer than 2021.03 version by throwing out following: arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: main-navss: {'type': 'object'} is not allowed for {'compatible': ['simple-mfd'], '#address-cells': [[2]], ..... This has already been correctly done for J7200, however was missed for other k3 SoCs. Fix that oversight. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210510145429.8752-1-nm@ti.com
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eb8f6194 |
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04-Mar-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
arm64: dts: ti: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems According to latest errata of J721e [1], HS400 mode is not supported in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2 subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode. Also, update the itap delay values for all the MMCSD subsystems according the latest J721e data sheet[2] [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf Fixes: cd48ce86a4d0 ("arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210305054104.10153-1-a-govindraju@ti.com
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4c842af3 |
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04-Mar-2021 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add ICSSG nodes Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are present on the K3 J721E SoCs. The two ICSSGs are identical to each other for the most part, with the ICSSG1 supporting slightly enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by a PRUSS subsystem node and other child nodes. These nodes are enabled by default. The ICSSGs on K3 J721E SoCs are revised versions of the ICSSG on the first AM65x SR1.0 SoCs. The PRU IRAMs are slightly smaller, and the IP includes two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB of IRAMs and leverage the same host interrupts as the regular PRU cores. All The ICSSG host interrupts intended towards the main Arm core are also shared with other processors on the SoC, and can be partitioned as per system integration needs. The ICSSG subsystem node contains the entire address space. The various sub-modules of the ICSSG are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores, two RTU cores, two Tx_PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), the Gigabit capable MII_G_RT and the CFG sub-module are represented as syscon nodes. The ICSSG CFG sub-module provides two internal clock muxes, and these are represented as children of the CFG child node 'clocks' by the 'coreclk-mux' and iepclk-mux' clk nodes. The default parents for these mux clocks are also defined using the assigned-clock-parents property. The DT nodes use all standard properties. The regs property in the PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU, RTU and Tx_PRU cores are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): ICSSG0 PRU0 Core : j7-pru0_0-fw ; PRU1 Core : j7-pru0_1-fw ICSSG0 RTU0 Core : j7-rtu0_0-fw ; RTU1 Core : j7-rtu0_1-fw ICSSG0 Tx_PRU0 Core : j7-txpru0_0-fw ; Tx_PRU1 Core : j7-txpru0_1-fw ICSSG1 PRU0 Core : j7-pru1_0-fw ; PRU1 Core : j7-pru1_1-fw ICSSG1 RTU0 Core : j7-rtu1_0-fw ; RTU1 Core : j7-rtu1_1-fw ICSSG1 Tx_PRU0 Core : j7-txpru1_0-fw ; Tx_PRU1 Core : j7-txpru1_1-fw Note: 1. The ICSSG INTC on J721E SoCs share all the host interrupts with other processors, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. 2. There are few more sub-modules like the Industrial Ethernet Peripherals (IEPs), MDIO, PWM, UART that do not have bindings and so will be added in the future. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210304160712.8452-3-s-anna@ti.com
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0cf73209 |
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15-Jan-2021 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3: mmc: fix dtbs_check warnings Now the dtbs_check produces below warnings sdhci@4f80000: clock-names:0: 'clk_ahb' was expected sdhci@4f80000: clock-names:1: 'clk_xin' was expected $nodename:0: 'sdhci@4f80000' does not match '^mmc(@.*)?$' Fix above warnings by updating mmc DT definitions to follow sdhci-am654.yaml bindings: - rename sdhci dt nodes to 'mmc@' - swap clk_xin/clk_ahb clocks, the clk_ahb clock expected to be defined first Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20210115193016.5581-1-grygorii.strashko@ti.com
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edb96779 |
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05-Jan-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210105151421.23237-3-kishon@ti.com
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0e3cfb86 |
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05-Jan-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions Cadence IP in J721E supports a maximum of 32 outbound regions. However commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") incorrectly added this as 16 outbound regions. Now that "cdns,max-outbound-regions" is an optional property with default value as 32, remove "cdns,max-outbound-regions" from endpoint DT node. (Since this doesn't impact existing functionality, it need not be backported to older kernels). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210105151421.23237-2-kishon@ti.com
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cd48ce86 |
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29-Nov-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes Add support for UHS modes for the SD card connected at sdhci1. This involves adding regulators for voltage switching and power cycling the SD card and removing the no-1-8-v property. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20201129175223.21751-3-nsekhar@ti.com
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09ff4e90 |
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29-Nov-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j721e-main: Add output tap delay values Add output tap delay values as given in the latest Data Manual[1], SPRSP36E, revised December 2019. [1] https://www.ti.com/lit/gpn/tda4vm Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20201129175223.21751-2-nsekhar@ti.com
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15ffd94a |
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27-Nov-2020 |
Sekhar Nori <nsekhar@ti.com> |
arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells There are couple of places where INTA interrupt controller lacks #interrupt-cells property. This leads to warnings of the type: arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider when building TI device-tree files with W=2 warning level. Fix these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com
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bfbf9be7 |
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13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the SoC dtsi. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com
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5d1bedf2 |
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13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j721e*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of j721e SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The only functional difference between the dtb generated is status='okay' is no longer necessary for mcasp10 and depends on the default state. NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20201113211826.13087-3-nm@ti.com
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cfbf17e6 |
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04-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node Fix the node address to follow the device tree convention. This fixes the dtc warning: <stdout>: Warning (simple_bus_reg): /bus@100000/dss@04a00000: simple-bus unit address format error, expected "4a00000" Fixes: 76921f15acc0 ("arm64: dts: ti: k3-j721e-main: Add DSS node") Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Link: https://lore.kernel.org/r/20201104222519.12308-1-nm@ti.com
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df445ff9 |
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28-Oct-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding main cluster node. Both the clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode) Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20201029033802.15366-7-s-anna@ti.com
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#
4e583388 |
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14-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Add PCIe device tree nodes (both RC and EP) for the four PCIe instances here. Also add the missing translations required in the "ranges" DT property of cbass_main to access all the four PCIe instances. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com
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#
c65176fd |
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18-Sep-2020 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j721e: Rename mux header and update macro names We intend to use one header file for SERDES MUX for all TI SoCs so rename the header file. The exsting macros are too generic. Prefix them with SoC name. While at that, add the missing configurations for completeness. Fixes: b766e3b0d5f6 ("arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux") Reported-by: Peter Rosin <peda@axentia.se> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20200918165930.2031-1-rogerq@ti.com
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#
e5c956c4 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
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#
dcccf770 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-*: Use generic pinctrl for node names Use pinctrl@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-6-nm@ti.com
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#
804a4cc7 |
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24-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add C71x DSP node The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. The following firmware name is used by default for the C71x core, and can be overridden in a board dts file if desired: C71x_0 DSP: j7-c71_0-fw Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com
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#
eb9a2a63 |
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24-Aug-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: C66x_0 DSP: j7-c66_0-fw C66x_1 DSP: j7-c66_1-fw Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-3-s-anna@ti.com
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#
8ebcaaae |
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26-Aug-2020 |
Keerthy <j-keerthy@ti.com> |
arm64: dts: ti: k3-j721e-main: Add crypto accelerator node Add crypto accelarator node for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites. [t-kristo@ti.com: Modifications based on introduction of yaml binding] Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200826082921.19143-3-t-kristo@ti.com
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#
8d523f09 |
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06-Aug-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings Update the INTA and INTR dt nodes to the latest DT bindings. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-12-lokeshvutla@ti.com
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#
4716053a |
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29-Jun-2020 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX The USB controllers can be connected to one of the 2 SERDESes using a MUX. Add a MUX controller node fot that. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
b766e3b0 |
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29-Jun-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
afd094eb |
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29-Jun-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes Add DT nodes for all instances of WIZ and SERDES modules. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
6e6972f9 |
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26-Jun-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controller The preferable name for gic-its is msi-controller, so rename it to fix dtbs_check warning: k3-j721e-common-proc-board.dt.yaml: interrupt-controller@1800000: gic-its@1820000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'reg': [[0, 25296896, 0, 65536]], 'socionext,synquacer-pre-its': [[16777216, 4194304]], 'msi-controller': True, '#msi-cells': [[1]]} Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
d0c72c77 |
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26-Jun-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-j721e-main: rename smmu node to iommu Rename smmu node to iommu to fix dtbs_check warning: k3-j721e-common-proc-board.dt.yaml: smmu@36600000: $nodename:0: 'smmu@36600000' does not match '^iommu@[0-9a-f]*' Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
303d6f62 |
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12-Jul-2020 |
Alexander A. Klimov <grandmaster@al2klimov.de> |
arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
461d6d05 |
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01-May-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: j721e-main: add main navss cpts node Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cae80943 |
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26-Sep-2019 |
Tero Kristo <t-kristo@ti.com> |
arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries Add DT entries for main domain watchdog0 and 1 instances. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
76921f15 |
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21-Apr-2020 |
Tomi Valkeinen <tomi.valkeinen@ti.com> |
arm64: dts: ti: k3-j721e-main: Add DSS node Add DSS node for J721E SoC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
1c4d3526 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j721e-main: Add McASP nodes Add the nodes for McASP 0-11 and keep them disabled because several required properties are not present as they are board specific. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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6f73c1e5 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j721e: DMA support Add the ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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515c0340 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss Secure proxy (NAVSS0_SEC_PROXY0) and smmu (NAVSS0_TCU) is part of the Navigator Subsystem. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
ab641f28 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation NAVSS is a subsystem containing different IPs, it is not really a bus. Change the compatible from "simple-bus" to "simple-mfd" to reflect that. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
3f03a58b |
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22-Nov-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-j721e-main: Add missing power-domains for smmu Add power-domains entry for smmu, so that the it is accessible as long as the driver is active. Without this device shutdown is throwing the below warning: "[ 44.736348] arm-smmu-v3 36600000.smmu: failed to clear cr0" Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
cb27354b |
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11-Dec-2019 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j721e: Add DT nodes for few peripherials Enable I2Cs, ADCs, OSPIs and UFS peripherals present on J721e. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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451555c8 |
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28-Oct-2019 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j721e-main: add USB controller nodes J721e has 2 USB super-speed controllers add them. The USB2 PHY doesn't need any configuration. USB3 PHY needs to be implemented using the Cadence Sierra PHY. This support will be added later. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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e6dc10f2 |
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19-Sep-2019 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: j721e-main: Add SDHCI nodes Add nodes for the 3 SDHCI instances present on TI's J721E device. instance 0 supports HS400 (8 bit bus widht, DDR, 400 MBps) while instances 1 and 2 support SDR104 (4 bit width, SDR, 100 MBps) as their highest speed modes. Currently, only High speed (50 MHz clock) has been enabled. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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56f18582 |
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24-Jul-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes The J721E Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A72 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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d6dabd6f |
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08-Aug-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address The gic-its node unit-address has an additional zero compared to the actual reg value. Fix it. Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Robert Tivy <rtivy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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7b472ced |
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22-Jul-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add hwspinlock node The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs. Add the DT node for this on J721E SoCs. The node is present within the Main NavSS block, and is added as a child node under the cbass_main_navss interconnect node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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248f3eae |
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09-Aug-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-j721e: Add gpio nodes in main domain There are 8 instances of gpio modules in main domain divided into 2 groups: - Group1: gpio0, gpio2, gpio4, gpio6 - Group2: gpio1, gpio3, gpio5, gpio7 Groups are created to provide protection between two different processor virtual worlds. There are x gpio lines coming out of each group. Each module in a group has equal x gpio lines pinned out. There is a top level mux for selecting the module instance for each pin coming out of group. Exactly one module can be selected to control the corresponding pin. This muxing can be controlled along the pad mux configuration registers. Group1 pins out 128 lines(8 banks). Group 2 pins out 36 lines(2 banks). Add DT nodes for each module instance in the main domain. Users should make sure that correct gpio instance is selected in their pad configuration. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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bf146a1a |
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29-Jul-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-j721e: Update the power domain cells Update the power-domain cells to 2 and mark all devices as exclusive. Main uart 0 is the debug console for processor boards and it is used by different software entities like u-boot, atf, linux simultaneously. So just mark main_uart0 as shared device for common processor board. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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073086fc |
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14-Jun-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain Main domain in J721E has the following interrupt controller instances: - Main Domain GPIO Interrupt router connected to gpio in main domain. - Under the Main Domain Navigator Subsystem(NAVSS) - Main Navss Interrupt Router connected to main navss inta and mailboxes. - Main Navss Interrupt Aggregator connected to main domain UDMASS Add DT nodes for the interrupt controllers available in main domain. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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1463a70d |
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30-May-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node Add the Interrupt controller node for the Interrupt Router present within the Main NavSS module. This Interrupt Router can route 192 interrupts to the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is reserved for the host ID A72_3 for hypervisor usecases, so the node is added only with 2 sets for the Linux kernel context (host id A72_2). This is specified through the ti,sci-rm-range-girq property. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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2d87061e |
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22-May-2019 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: Add Support for J721E SoC The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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