arm64: dts: ti: beagle*: Add MIT license along with GPL-2.0

Modify license to include dual licensing as GPL-2.0-only OR MIT
license for device trees belonging to BeagleBoard.org Foundation
platforms. This allows for Linux kernel device tree to be used in
other Operating System ecosystems such as Zephyr or FreeBSD.

While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync
with latest SPDX conventions (GPL-2.0 is deprecated).

While at this, update the copyright year to sync with current year
to indicate license change.

Cc: Ayush Singh <ayushdevel1325@gmail.com>
Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Robert Nelson <robertcnelson@gmail.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Wadim Egorov <w.egorov@phytec.de>

Acked-by: Ayush Singh <ayushdevel1325@gmail.com>
Acked-by: Jason Kridner <jkridner@beagleboard.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Robert Nelson <robertcnelson@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240122145539.194512-14-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Do not split single items

Each "mboxes" item is composed of two cells. It seems these got split
as they appeared to be two items in an array, but are actually a single
two-cell item. Rejoin these cells.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240123222536.875797-8-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board level

C6x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with both mboxes and
memory-region information.

As theses only known about at the board integration level, these nodes
should only be enabled when provided with this information.

Disable the C6x DSP nodes in the dtsi files and only enable the ones that
are given the required mboxes and memory-region on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Hari Nagalla <hnagalla@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230809180145.53158-3-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board level

C7x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with both mboxes and
memory-region information.

As theses only known about at the board integration level, these nodes
should only be enabled when provided with this information.

Disable the C7x DSP nodes in the dtsi files and only enable the ones that
are given the required mboxes and memory-region on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Hari Nagalla <hnagalla@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230809180145.53158-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level

TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and/or
device information.

Disable the TSCADC nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-12-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level

GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

Disable the GPIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-9-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level

OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

As the attached OSPI device is only known about at the board integration
level, these nodes should only be enabled when provided with this
information.

Disable the OSPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-6-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: k3-j721e: Enable SDHCI nodes at the board level

SDHCI nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended.

As the attached SD/eMMC is only known about at the board integration level,
these nodes should only be enabled when provided with this information.

Disable the SDHCI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

arm64: dts: ti: Unify pin group node names for make dtbs checks

Prepare for pinctrl-single yaml binding and unify pin group node names.

Let's standardize on pin group node naming ending in -pins. As we don't
necessarily have a SoC specific compatible property for pinctrl-single.
I'd rather not add a pattern match for pins somewhere in the name for all
the users.

Trying to add matches for pins-default will be futile as on the earlier
SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so
on that would need to be matched.

And as the node is a pin group, let's prefer to use naming -pins rather
than -pin as more pins may need to be added to the pin group later on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
[vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmux

Define the wakeup uart pin-mux for completeness. This allows the
device tree usage in bootloader and firmwares that can configure the
same appropriately.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array

When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Move eeprom WP gpio pinctrl to eeprom node

Move the eeprom WP GPIO mux configuration to be part of the eeprom node
instead of the I2C node.

Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Move camera gpio pinctrl to gpio node

Move the GPIO mux configuration needed for camera module to work to the
GPIO node instead of the I2C node.

Camera nodes are maintained as overlay files, but the common mux is
always needed to ensure that camera probes fine and ensuring the mux
is configured as part of the GPIO module allows for the multiple
overlay files to be simpler.

Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level

MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.

As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.

Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level

PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.

As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes

These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.

Examples should go in the bindings or other documentation.

Remove this node.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status

Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
addition went in at around the same time and must have missed that
change so the mailboxes are not re-enabled. Do that here.

Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arm64: dts: ti: Add k3-j721e-beagleboneai64

BeagleBoard.org BeagleBone AI-64 is an open source hardware single
board computer based on the Texas Instruments TDA4VM SoC featuring
dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
floating-point VLIW DSPs, 3x dual Arm Cortex-R5 co-processors,
2x 6-core Programmable Real-Time Unit and Industrial Communication
SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
BeagleBone expansion headers.

This board family can be indentified by the BBONEAI-64-B0 in the
at24 eeprom:

[aa 55 33 ee 01 37 00 10 2e 00 42 42 4f 4e 45 41 |.U3..7....BBONEA|]
[49 2d 36 34 2d 42 30 2d 00 00 42 30 30 30 37 38 |I-64-B0-..B00078|]

https://beagleboard.org/ai-64
https://git.beagleboard.org/beagleboard/beaglebone-ai-64

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Reviewed-by: Andrew Davis <afd@ti.com>
CC: Nishanth Menon <nm@ti.com>
CC: Vignesh Raghavendra <vigneshr@ti.com>
CC: Tero Kristo <kristo@kernel.org>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221118163139.3592054-2-robertcnelson@gmail.com