#
0fa8b0e2 |
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14-Feb-2024 |
Bhavya Kapoor <b-kapoor@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from mcu_uart0 Clock-frequency property is already present in mcu_uart0 node of the k3-j7200-mcu-wakeup.dtsi file. Thus, remove redundant clock-frequency property from mcu_uart0 node. Fixes: 3709ea7f960e ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-3-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
566feddd |
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14-Feb-2024 |
Bhavya Kapoor <b-kapoor@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and mcu_uart0 WKUP_PADCONFIG registers for wkup_uart0 and mcu_uart0 lies under wkup_pmx2 for J7200. Thus, modify pinmux for both of them. Fixes: 3709ea7f960e ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-2-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
b87c44dd |
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22-Jan-2024 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j7200: Add MIT license along with GPL-2.0 Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: Esteban Blanc <eblanc@baylibre.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Esteban Blanc <eblanc@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
6b80695f |
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30-Jan-2024 |
Bhavya Kapoor <b-kapoor@ti.com> |
arm64: dts: ti: k3-j7200: Add support for multiple CAN instances CAN instances 0 and 1 in the mcu domain are brought on the common processor board through headers J30 and J31 respectively. Thus, add their respective transceivers 1 and 2 dt nodes to add support for these CAN instances. CAN instance 3 in the main domain is brought on the common processor board through header J27. The CAN High and Low lines from the SoC are routed through a mux on the SoM. The select lines need to be set for the CAN signals to get connected to the transceiver 3 on the common processor board. Therefore, add transceiver dt nodes to add support for this CAN instance. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240130102044.120483-4-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
0b16abe7 |
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23-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Remove PCIe endpoint node This node is an example node for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124183659.149119-2-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
1b63a1b4 |
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23-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level PCIe node defined in the top-level J7200 SoC dtsi file is incomplete and will not be functional unless it is extended with a SerDes PHY. As the PHY and mode is only known at the board integration level, this node should only be enabled when provided with this information. Disable the PCIe node in the dtsi files and only enable when it is actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124183659.149119-1-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
d9fe476d |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-11-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
013b7dd3 |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level J7200 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
8d08d7aa |
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21-Jul-2023 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: Use local header for SERDES MUX idle-state values The DTS uses constants for SERDES MUX idle state values which were earlier provided as bindings header. But they are unsuitable for bindings. So move these constants in a header next to DTS. Also add J784S4 SERDES4 lane definitions which were missed earlier. Suggested-by: Nishanth Menon <nm@ti.com> Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/ Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Roger Quadros <rogerq@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
a4956811 |
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15-Jun-2023 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: Unify pin group node names for make dtbs checks Prepare for pinctrl-single yaml binding and unify pin group node names. Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users. Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched. And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on. Signed-off-by: Tony Lindgren <tony@atomide.com> [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
c4ba159f |
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11-Jun-2023 |
Udit Kumar <u-kumar1@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board level Define aliases at board level Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
3709ea7f |
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11-Jun-2023 |
Udit Kumar <u-kumar1@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
7f58e2b4 |
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11-Jun-2023 |
Udit Kumar <u-kumar1@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
a6550e25 |
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06-Jun-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230606182220.3661956-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
be8be0d0 |
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13-May-2023 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux J7200 common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
3d011933 |
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18-Apr-2023 |
Keerthy <j-keerthy@ti.com> |
arm64: dts: ti: k3-j7200: Fix physical address of pin wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac445e9 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230419040007.3022780-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
f920c49f |
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19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
9ae21ac4 |
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18-Jan-2023 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-j7200: Fix wakeup pinmux range The WKUP_PADCONFIG register region in J7200 has multiple non-addressable regions, split the existing wkup_pmx region as follows to avoid the non-addressable regions and include all valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119042622.22310-1-vaishnav.a@ti.com
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#
a9ed915c |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Enable I2C nodes at the board level I2C nodes defined in the top-level J7200 SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-7-afd@ti.com
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#
dae322f8 |
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20-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-j7200: Enable UART nodes at the board level UART nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-6-afd@ti.com
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#
0d0a0b44 |
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19-Sep-2022 |
Matt Ranostay <mranostay@ti.com> |
arm64: dts: ti: k3-j7200: fix main pinmux range Range size of 0x2b4 was incorrect since there isn't 173 configurable pins for muxing. Additionally there is a non-addressable region in the mapping which requires splitting into two ranges. main_pmx0 -> 67 pins main_pmx1 -> 3 pins Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220919205723.8342-1-mranostay@ti.com
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#
2cf3213d |
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25-Sep-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add j7200-evm compatible Add j7200-evm compatible to the board to allow the board to distinguish itself from other platforms that may be added in the future. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210925201430.11678-5-nm@ti.com
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69db725c |
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26-May-2021 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction The MCU RGMII MCU_RGMII1_TXC pin is defined as input by mistake, although this does not make any difference functionality wise it's better to update to avoid confusion. Hence fix MCU RGMII MCU_RGMII1_TXC pin pinmux definitions to be an output in K3 am654x/j721e/j7200 board files. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210526132041.6104-1-grygorii.strashko@ti.com
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94374990 |
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25-Mar-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems The following speed modes are now supported in J7200 SoC, - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1]. - UHS-I speed modes in MMCSD1 subsystem [1]. Add support for UHS-I modes by adding voltage regulator device tree nodes and corresponding pinmux details, to power cycle and voltage switch cards. Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1 device tree nodes. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210326064120.31919-4-a-govindraju@ti.com
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#
f4cc7daf |
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25-Mar-2021 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules There are 6 gpio instances inside SoC with 2 groups as show below: Group one: wkup_gpio0, wkup_gpio1 Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6 Only one instance from each group can be used at a time. So use main_gpio0 and wkup_gpio0 in current linux context and disable the rest of the nodes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20210326064120.31919-3-a-govindraju@ti.com
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3a6319df |
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05-Jan-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe x2 lane PCIe slot in the common processor board is enabled and connected to j7200 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210105151421.23237-7-kishon@ti.com
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#
429c0259 |
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05-Jan-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe and QSGMII (multi-link SERDES). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210105151421.23237-6-kishon@ti.com
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#
2eefbf5f |
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20-Nov-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3 The i2c1 devices on the CPB are _not_ connected to the SoC, they are not usable with the J7200 SOM. Correct the expander name from exp4 to exp3 and at the same time add the line names as well. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20201120073533.24486-3-peter.ujfalusi@ti.com
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#
b6633d77 |
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20-Nov-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM The J7200 SOM have additional io expander which is used to control several SOM level muxes to make sure that the correct signals are routed to the correct pin on the SOM <-> CPB connectors. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com
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#
4cc34aa8 |
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13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved" Follow the device tree standards that states to set the status="reserved" if an device is operational, but used by a non-linux firmware in the system. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20201113211826.13087-6-nm@ti.com
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#
e6b45168 |
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28-Oct-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20201029050950.4500-1-vigneshr@ti.com
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#
bbcb0522 |
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30-Sep-2020 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support The board uses lane 3 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, QSGMII and USB super-speed. It has been chosen to use PCI2 and QSGMII as default. So restrict USB0 to high-speed mode. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com
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e38a45b0 |
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30-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function First two lanes of SERDES is connected to PCIe, third lane is connected to QSGMII and the last lane is connected to USB. However, Cadence torrent SERDES doesn't support more than 2 protocols at the same time. Configure it only for PCIe and QSGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
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a2178b83 |
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24-Sep-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card Add support for the eMMC and SD card connected on the common processor board sdhci0 is connected to an eMMC while sdhci1 is connected to the micro SD slot. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com
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e25889f8 |
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23-Sep-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and also add the pinmux corresponding to these I2C instances. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com
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fc3b1550 |
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23-Sep-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
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26bd3f31 |
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14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Add support for J7200 Common Processor Board Add support for J7200 Common Processor Board. The EVM architecture is very similar to J721E as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Note: * The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. * Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. * All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
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