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d74d8cde |
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25-Nov-2023 |
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> |
arm64: dts: renesas: r9a09g011: Add missing space in compatible Add missing space in compatible property and align style with rest of the file. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231125233242.237660-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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ba81bf44 |
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21-Jun-2023 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Add CSI nodes The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI) IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only allowed access to CSI0 and CSI4. This commit adds SoC specific device tree support for CSI0 and CSI4. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230622113341.657842-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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670e2a8b |
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21-Jan-2023 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a09g011: Add USB3 DRD, device and host nodes This patch add usb3 host and peripheral device node as child of usb3 drd node to RZ/V2M SoC dtsi. The host/device needs to issue reset release on DRD module before accessing host/device registers. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230121145853.4792-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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cf67b319 |
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18-Jan-2023 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Add PWC support The RZ/V2M SoC contains an External Power Sequence Controller (PWC) module. This module provides an external power supply on/off sequence, on/off signal for the LPDDR4 core power supply, General Purpose Outputs, and key input signals. This patch adds PWC support to the SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230118144747.24968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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11ffdcdf |
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18-Jan-2023 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Reword ethernet status Although of_fdt_device_is_available returns true when the DT property "status" is assigned "ok" or "okay", and false for every other value, it's become common practice to assign "disabled" when we want of_fdt_device_is_available to return false. For some reason, the status property of the ethernet node was assigned "disable" when originally added to the kernel. Change it to "disabled" for consistency. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230118135259.19249-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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36aa3eee |
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13-Dec-2022 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface. Add the relevant nodes to the SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221213230129.549968-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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b9e88ba6 |
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16-Nov-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a09g011: Add system controller node Add system controller node to RZ/V2M SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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c6b1737f |
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10-Nov-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a09g011: Add L2 Cache node The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache. Add L2 Cache node to SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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753a4ae1 |
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03-Nov-2022 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Add watchdog node The r9a09g011 (a.k.a. RZ/V2M) comes with two watchdog IPs, but Linux is only allowed one. Add a node for the watchdog allowed to Linux to the SoC specific dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221103223956.50575-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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2ac90991 |
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07-Nov-2022 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings The preferred form for Renesas' compatible strings is: "<vendor>,<family>-<module>" Somehow the compatible string for the r9a09g011 I2C IP was upstreamed as renesas,i2c-r9a09g011 instead of renesas,r9a09g011-i2c, which is really confusing, especially considering the generic fallback is renesas,rzv2m-i2c. The first user of renesas,i2c-r9a09g011 in the kernel is not yet in a kernel release, it will be in v6.1, therefore it can still be fixed in v6.1. Even if we don't fix it before v6.2, I don't think there is any harm in making such a change. s/renesas,i2c-r9a09g011/renesas,r9a09g011-i2c/g for consistency. Fixes: 54ac6794df9d ("arm64: dts: renesas: r9a09g011: Add i2c nodes") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221107165027.54150-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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278f5015 |
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03-Nov-2022 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
arm64: dts: renesas: r9a09g011: Fix unit address format error Although the HW User Manual for RZ/V2M states in the "Address Map" section that the interrupt controller is assigned addresses starting from 0x82000000, the memory locations from 0x82000000 0x0x8200FFFF are marked as reserved in the "Interrupt Controller (GIC)" section and are currently not used by the device tree, leading to the below warning: arch/arm64/boot/dts/renesas/r9a09g011.dtsi:51.38-63.5: Warning (simple_bus_reg): /soc/interrupt-controller@82000000: simple-bus unit address format error, expected "82010000" Fix the unit address accordingly. Fixes: fb1929b98f2e ("arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221103230648.53748-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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54ac6794 |
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19-Aug-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
arm64: dts: renesas: r9a09g011: Add i2c nodes Add device nodes for the I2C controllers that are not assigned to the ISP. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220819193944.337599-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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73ca80da |
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04-Aug-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
arm64: dts: renesas: r9a09g011: Add pinctrl node Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220804190846.128370-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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4872ca1f |
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17-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
arm64: dts: renesas: r9a09g011: Add ethernet nodes Add Ethernet nodes to SoC dtsi. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220517081645.3764-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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fb1929b9 |
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04-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220504094456.24386-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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