#
62f87a3c |
|
29-Mar-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add DisplayPort controller Add the node for the DisplayPort controller found on the SM6350 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
fd5afa5d |
|
19-Feb-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add Crypto Engine Add crypto engine (CE) and CE BAM related nodes and definitions for this SoC. For reference: [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240219-sm6350-qce-v2-1-7acb8838f248@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
f0116881 |
|
19-Feb-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs The code in qcom_q6v5_init() requests the "wdog" IRQ as IRQF_TRIGGER_RISING. If dt defines the interrupt type as LEVEL_HIGH then the driver will have issues getting the IRQ again after probe deferral with an error like: irq: type mismatch, failed to map hwirq-14 for interrupt-controller@b220000! Fix that by updating the devicetrees to use IRQ_TYPE_EDGE_RISING for these interrupts, as is already used in most dt's. Also the driver was already using the interrupts with that type. Fixes: 3658e411efcb ("arm64: dts: qcom: sc7280: Add ADSP node") Fixes: df62402e5ff9 ("arm64: dts: qcom: sc7280: Add CDSP node") Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Fixes: 8eb5287e8a42 ("arm64: dts: qcom: sm6350: Add CDSP nodes") Fixes: efc33c969f23 ("arm64: dts: qcom: sm6350: Add ADSP nodes") Fixes: fe6fd26aeddf ("arm64: dts: qcom: sm6375: Add ADSP&CDSP") Fixes: 23a8903785b9 ("arm64: dts: qcom: sm8250: Add remoteprocs") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240219-remoteproc-irqs-v1-1-c5aeb02334bd@fairphone.com [bjorn: Added fixes references] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
891af1aa |
|
16-Feb-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU Add the description for the display panel found on this phone. Unfortunately the LCDB module on PM6150L isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-4-a556e4b79640@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
2abe4a31 |
|
16-Feb-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Remove "disabled" state of GMU The GMU won't probe without GPU being enabled, so we can remove the disabled status so we don't have to explicitly enable the GMU in all the devices that enable GPU. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-3-a556e4b79640@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
fc48bb31 |
|
16-Feb-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add interconnect for MDSS Add the definition for the interconnect used in the display subsystem. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240216-sm6350-interconnect-v1-1-9d55667c06ca@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
68f9fcba |
|
30-Jan-2024 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
arm64: dts: qcom: sm6350: Fix UFS PHY clocks QMP PHY used in SM6350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-10-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
64628795 |
|
24-Jan-2024 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add tsens thermal zones Add the definitions for the various thermal zones found on the SM6350 SoC. Hooking up GPU and CPU cooling can limit the clock speeds there to reduce the temperature again to good levels. Most thermal zones only have one critical temperature configured at 125°C which can be mostly considered a placeholder until those zones can be hooked up to cooling. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240124-sm6350-tsens-v1-1-d37ec82140af@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
7c9afa1f |
|
25-Jan-2024 |
Krishna Kurapati <quic_kriskura@quicinc.com> |
arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Also modify order of interrupts in accordance to bindings update. Modifying the order of these interrupts is harmless as the driver tries to get these interrupts from DT by name and not by index. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-4-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
8e89beb3 |
|
04-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
arm64: dts: qcom: sm6350: switch UFS QMP PHY to new style of bindings Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
5b84bb2b |
|
06-Nov-2023 |
Douglas Anderson <dianders@chromium.org> |
arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.8.Ic1d4402e99c70354d501ccd98105e908a902f671@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
90282403 |
|
11-Aug-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-6-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
1df6b32e |
|
11-Jul-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Add BWMONs Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm6350. There are 3 more NPU BWMONs, but these are skipped for now. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230711-topic-sm638250_bwmon-v1-4-bd4bb96b0673@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
c86b97a7 |
|
18-Jun-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: sm6350: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm6350-sony-xperia-lena-pdx213.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230618114442.140185-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
26c71d31 |
|
14-Jun-2023 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add DPU1 nodes Add nodes required to enable MDSS/DPU1 on SM6350. There seem to be no additional changes required to support the derivative SoCs, such as SM7225. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-7-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
44bcded2 |
|
14-Jun-2023 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Fix ZAP region The previous ZAP region definition was wrong. Fix it. Note this is not a device-specific fixup, but a fixup to the generic PIL load address. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-6-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
bd9b7675 |
|
14-Jun-2023 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add GPU nodes Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
5b1e5d9a |
|
14-Jun-2023 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add QFPROM node Add a node for the QFPROM NVMEM hw and define the GPU fuse. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-4-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
75a511b1 |
|
14-Jun-2023 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add GPUCC node Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
#
b179f35b |
|
12-May-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: add uart1 node Add the node describing uart1 incl. opp table and pinctrl. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230421-fp4-bluetooth-v2-3-3de840d5483e@fairphone.com
|
#
255c53df |
|
31-May-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-7-b4a985f57b8b@linaro.org
|
#
ade89bc0 |
|
31-May-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Add PSCI idle states Add the PSCI idle states so that the CPU (among other things) can reach lower power states. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-2-b4a985f57b8b@linaro.org
|
#
fbd47f83 |
|
16-May-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Move wifi node to correct place Somehow wifi was placed further up in the file than where it should be. Move it down so the nodes are sorted by reg again. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516-sm6350-order-v1-1-5c3b7c4cd761@fairphone.com
|
#
9c6e72fb |
|
15-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: add missing cache properties Add required cache-level and cache-unified properties to fix warnings like: qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
|
#
64917707 |
|
07-Mar-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org
|
#
e18b8295 |
|
06-Mar-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: drop redundant line breaks Remove trailing, redundant line breaks. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org
|
#
65d9975e |
|
14-Mar-2023 |
Manivannan Sadhasivam <mani@kernel.org> |
arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org
|
#
afa34380 |
|
14-Feb-2023 |
Manivannan Sadhasivam <mani@kernel.org> |
arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230215070400.5901-4-manivannan.sadhasivam@linaro.org
|
#
5ed2b638 |
|
23-Jan-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Use specific qmpphy compatible The sc7180 phy compatible works fine for some cases, but it turns out sm6350 does need proper phy configuration in the driver, so use the newly added sm6350 compatible. Because the sm6350 compatible is using the new binding, we need to change the node quite a bit to match it. This fixes qmpphy init when no USB cable is plugged in during bootloader stage. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com
|
#
033fb15f |
|
20-Jan-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add CCI nodes Add nodes for the two CCI blocks found on SM6350. The first contains two i2c busses and while the second one might also contains two busses, the downstream kernel only has one configured, and some boards use the GPIOs for the potential cci1_i2c1 one other purposes, so leave that one unconfigured. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213-sm6350-cci-v2-3-15c2c14c34bb@fairphone.com
|
#
4ab96c9c |
|
20-Jan-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add camera clock controller Add a node for the camcc found on SM6350 SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213-sm6350-cci-v2-2-15c2c14c34bb@fairphone.com
|
#
f48dbb34 |
|
02-Jan-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Pad addresses to 8 hex digits Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-9-konrad.dybcio@linaro.org
|
#
aed7154a |
|
04-Jan-2023 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: add IPA node IPA is used for mobile data. Add a node describing it. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104193759.3286014-2-elder@linaro.org
|
#
bba95227 |
|
04-Jan-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Set up DDR & L3 scaling Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. DDR clock rates come from the vendor kernel. Available values from the HW LUT: 300000000 556800000 652800000 806400000 844800000 940800000 1132800000 1209600000 1286400000 1401600000 1459200000 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
|
#
e17a8065 |
|
04-Jan-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Add OSM L3 node Enable the OSM block responsible for scaling the L3 cache. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104171643.1004054-2-konrad.dybcio@linaro.org
|
#
bb99820d |
|
13-Dec-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: rename AOSS QMP nodes The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is now handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "power-management". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org
|
#
9435294c |
|
07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: qcom: Update cache properties The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> [bjorn: Moved "qcom" to $subject prefix] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
|
#
3b2ff50d |
|
10-Dec-2022 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
arm64: dts: qcom: sm6350: Fix up the ramoops node Fix up the ramoops node to make it match bindings and style: - remove "removed-dma-pool" - don't pad size to 8 hex digits - change cc-size to ecc-size so that it's used - increase ecc-size from to 16 - remove the zeroed ftrace-size Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Reported-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221210102600.589028-1-konrad.dybcio@linaro.org
|
#
347b9491 |
|
11-Nov-2022 |
Johan Hovold <johan+linaro@kernel.org> |
arm64: dts: qcom: sm6350: fix USB-DP PHY registers When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes") Cc: stable@vger.kernel.org # 5.16 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111094729.11842-2-johan+linaro@kernel.org
|
#
7372b944 |
|
30-Oct-2022 |
Marijn Suijten <marijn.suijten@somainline.org> |
arm64: dts: qcom: sm6350: Add apps_smmu with streamID to SDHCI 1/2 nodes When enabling the APPS SMMU the mainline driver reconfigures the SMMU from its bootloader configuration, losing the stream mapping for (among which) the SDHCI hardware and breaking its ADMA feature. This feature can be disabled with: sdhci.debug_quirks=0x40 But it is of course desired to have this feature enabled and working through the SMMU. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221030073232.22726-11-marijn.suijten@somainline.org
|
#
a5d0314b |
|
30-Oct-2022 |
Marijn Suijten <marijn.suijten@somainline.org> |
arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2 Use the generic pin functions specifically for sdc2. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221030073232.22726-3-marijn.suijten@somainline.org
|
#
e10d451e |
|
30-Oct-2022 |
Marijn Suijten <marijn.suijten@somainline.org> |
arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2 Make sure the SDHCI hardware is properly reset before interacting with it, to protect against any possibly indeterminate state left by the bootloader. Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221030073232.22726-2-marijn.suijten@somainline.org
|
#
95fade40 |
|
26-Oct-2022 |
Johan Hovold <johan+linaro@kernel.org> |
arm64: dts: qcom: sm6350: drop bogus DP PHY clock The QMP pipe clock is used by the USB part of the PHY so drop the corresponding properties from the DP child node. Fixes: 23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026152511.9661-3-johan+linaro@kernel.org
|
#
448f5a00 |
|
12-Sep-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: sm6350: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220912061746.6311-36-krzysztof.kozlowski@linaro.org
|
#
9f0149ca |
|
12-Aug-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add GPI DMA nodes Add nodes for the gpi_dma0 and gpi_dma1 which are (optionally) used for various i2c busses based on the qup firmware configuration. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812082721.1125759-4-luca.weiss@fairphone.com
|
#
38c5c4fe |
|
25-May-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add interconnect support Add all the different NoC providers that are found in SM6350 and populate different nodes that use the interconnect properties. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220525144404.200390-6-luca.weiss@fairphone.com
|
#
7a9016db |
|
07-May-2022 |
Marijn Suijten <marijn.suijten@somainline.org> |
arm64: dts: qcom: sm6350: Replace literal rpmhpd indices with constants It seems the SM6350_CX definition was temporarily replaced with its literal value 0 in 1797e1c9a95c ("arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes") to prevent a dependency on the qcom-rpmpd.h header patch being available prior to this DT patch being applied, similar to c23f1b77358c ("arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX"). However, unlike the revert of that in the sm6125 tree the next merge window around in a90b8adfa2dd ("Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX""), this has not yet happened for sm6350: replace them back now that the definitions are definitely available. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220507224645.2238421-1-marijn.suijten@somainline.org
|
#
21857088 |
|
06-Jul-2022 |
Douglas Anderson <dianders@chromium.org> |
Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes" This reverts commit afcbe252e9c19161e4d4c95f33faaf592f1de086. The commit in question caused my sc7280-herobrine-herobrine-r1 board not to boot anymore. This shouldn't be too surprising since the driver is relying on the name "cqhci". The issue seems to be that someone decided to change the names of things when the binding moved from .txt to .yaml. We should go back to the names that the bindings have historically specified. For some history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci memory ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc: sdhci-msm: Add CQE reg map"). Fixes: afcbe252e9c1 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
|
#
afcbe252 |
|
14-May-2022 |
Bhupesh Sharma <bhupesh.sharma@linaro.org> |
arm64: dts: qcom: Fix 'reg-names' for sdhci nodes Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with ordering of 'reg-names' as various possible combinations are possible for different qcom SoC dts files. Fix the same by updating the offending 'dts' files. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220514215424.1007718-6-bhupesh.sharma@linaro.org
|
#
96bb736f |
|
14-May-2022 |
Bhupesh Sharma <bhupesh.sharma@linaro.org> |
arm64: dts: qcom: Fix sdhci node names - use 'mmc@' Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'sdhci@' convention used for specifying the sdhci nodes. The generic mmc bindings expect 'mmc@' format instead. Fix the same. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> [bjorn: Moved non-arm64 changes to separate commit] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
|
#
458ebdbb |
|
25-Jun-2022 |
David Heidelberg <david@ixit.cz> |
arm64: dts: qcom: timer should use only 32-bit size There's no reason the timer needs > 32-bits of address or size. Since we using 32-bit size, we need to define ranges properly. Fixes warnings as: ``` arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml ``` Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz
|
#
0e3e6546 |
|
27-Jun-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: align OPP table names with DT schema DT schema expects names of operating points tables to start with "opp-table": ipq6018-cp01-c1.dtb: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$' Use hyphens instead of underscores, fix the names to match DT schema or remove the prefix entirely when it is not needed. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220627093250.84391-1-krzysztof.kozlowski@linaro.org
|
#
8d5fd4e4 |
|
04-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: align DWC3 USB clocks with DT schema Align order of clocks and their names with Qualcomm DWC3 USB DT schema. No functional impact expected. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
fc0e7dd6 |
|
11-Apr-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: do not use underscore in BCM node name Align BCM voter node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411085935.130072-3-krzysztof.kozlowski@linaro.org
|
#
48cc9bb1 |
|
25-Mar-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add wifi node Add a node describing the wifi hardware found on sm6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220325101841.172304-1-luca.weiss@fairphone.com
|
#
5a814af5 |
|
21-Mar-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add UFS nodes Add the necessary nodes for UFS and its PHY. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220321133318.99406-6-luca.weiss@fairphone.com
|
#
7be9f3ae |
|
08-Apr-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add I2C busses Add nodes for the I2C busses on sm6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220408114205.234635-2-luca.weiss@fairphone.com
|
#
9e5c45a5 |
|
08-Apr-2022 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Fix naming of uart9 The uart9 was previously mistakenly called uart2. Fix this. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220408114205.234635-1-luca.weiss@fairphone.com
|
#
8eb5287e |
|
13-Dec-2021 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add CDSP nodes Add the required nodes for booting the CDSP on sm6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082208.21492-8-luca.weiss@fairphone.com
|
#
efc33c96 |
|
13-Dec-2021 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add ADSP nodes Add the required nodes for booting the ADSP on sm6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082208.21492-6-luca.weiss@fairphone.com
|
#
489be59b |
|
13-Dec-2021 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Add MPSS nodes Add the required nodes for booting the MPSS on sm6350. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082208.21492-4-luca.weiss@fairphone.com
|
#
f56498fc |
|
13-Dec-2021 |
Luca Weiss <luca.weiss@fairphone.com> |
arm64: dts: qcom: sm6350: Fix validation errors Sort clocks and interrupts as specified in the docs and remove the stray property #power-domain-cells from aoss_qmp to solve dtbs_check validation errors. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082614.22651-11-luca.weiss@fairphone.com
|
#
9e7f7b65 |
|
13-Nov-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as the &pdc-nth range of the main interrupt controller (GIC). Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211114012755.112226-5-konrad.dybcio@somainline.org
|
#
cd10fb79 |
|
07-Oct-2021 |
Luca Weiss <luca@z3ntu.xyz> |
arm64: dts: qcom: sm6350: add debug uart Add the necessary nodes for the debug uart on SM6350. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-8-luca@z3ntu.xyz
|
#
4ef13f7f |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add apps_smmu and assign iommus prop to USB1 Add a node for the APPS SMMU to allow for managing memory access to peripherals such as the USB controller. While at it, add iommus property to the USB1 node to make sure its registers can be accessed, as they seem to be gated by default. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-15-konrad.dybcio@somainline.org
|
#
1797e1c9 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes Add SDHCI1/2 nodes for eMMC and uSD card respectively. Do note that most SM6350 devices seem to come with UFS. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Replaced SM6350_CX with its constant value] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org
|
#
9264d3c8 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Add RPMHPD node, its OPP table and BCM voter to prepare for performance level voting. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-13-konrad.dybcio@somainline.org
|
#
574af545 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add PRNG node Add a node for the PRNG to enable hw-accelerated pseudo-random number generation. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-12-konrad.dybcio@somainline.org
|
#
001eaf95 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add SPMI bus Add a node for SPMI to allow for communication with on-board PMICs. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-11-konrad.dybcio@somainline.org
|
#
8fe2e0d9 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add AOSS_QMP Add a node for AOSS_QMP in preparation for remote processor enablement. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-10-konrad.dybcio@somainline.org
|
#
25e0ae68 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add TSENS nodes Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-9-konrad.dybcio@somainline.org
|
#
3cc41541 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add cpufreq-hw support Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org
|
#
23737b95 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add USB1 nodes Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and SC7180 IP, so no additional code porting is required. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Renamed dwc3 node "usb"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org
|
#
538f4bcd |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add TLMM block node Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org
|
#
30de1108 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add GCC node Add and configure GCC node to allow for referencing GCC-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org
|
#
985e02e7 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add RPMHCC node Add RPMHCC node to allow for referencing RPMH-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-4-konrad.dybcio@somainline.org
|
#
ced2f0d7 |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: sm6350: Add LLCC node Add a node for LLCC with SM6350-specific compatible. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-3-konrad.dybcio@somainline.org
|
#
5f82b9cd |
|
23-Sep-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
arm64: dts: qcom: Add SM6350 device tree Add a base DT for SM6350 SoC Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org
|