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f2f8115f |
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21-Dec-2021 |
Roger Quadros <rogerq@kernel.org> |
memory: omap-gpmc: Use a compatible match table when checking for NAND controller As more compatibles can be added to the GPMC NAND controller driver use a compatible match table. Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20211221131757.2030-4-rogerq@kernel.org [krzysztof: remove "is_nand" variable] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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d2912cb1 |
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04-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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0d96a4f6 |
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06-Oct-2017 |
Ladislav Michl <ladis@linux-mips.org> |
memory: omap-gpmc: Drop gpmc_status This field is no longer used, drop it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Roger Quadros <rogerq@ti.com>
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086c321e |
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10-Oct-2017 |
Ladislav Michl <ladis@linux-mips.org> |
mtd: nand: omap2: Remove omap_nand_platform_data As driver is now configured using DT, omap_nand_platform_data structure is no longer needed. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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10f22ee3 |
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06-Aug-2015 |
Roger Quadros <rogerq@ti.com> |
mtd: nand: omap2: Implement NAND ready using gpiolib The GPMC WAIT pin status are now available over gpiolib. Update the omap_dev_ready() function to use gpio instead of directly accessing GPMC register space. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Tony Lindgren <tony@atomide.com>
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9e694621 |
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07-Aug-2015 |
Roger Quadros <rogerq@ti.com> |
memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs GPMC_STATUS register is private to the GPMC module and must not be accessed directly by NAND driver through the gpmc_regs. They must use gpmc_omap_get_nand_ops() instead. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
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c9711ec5 |
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20-May-2014 |
Roger Quadros <rogerq@ti.com> |
mtd: nand: omap: Clean up device tree support Move NAND specific device tree parsing to NAND driver. The NAND controller node must have a compatible id, register space resource and interrupt resource. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com>
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c509aefd |
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05-Aug-2015 |
Roger Quadros <rogerq@ti.com> |
mtd: nand: omap: Use gpmc_omap_get_nand_ops() to get NAND registers Deprecate nand register passing via platform data and use gpmc_omap_get_nand_ops() instead. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com>
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fef775ca |
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10-Sep-2014 |
Ezequiel García <ezequiel@vanguardiasur.com.ar> |
nand: omap2: Add support for flash-based bad block table This commit adds a new platform-data boolean property that enables use of a flash-based bad block table. This can also be enabled by setting the 'nand-on-flash-bbt' devicetree property. If the flash BBT is not enabled, the driver falls back to use OOB bad block markers only, as before. If the flash BBT is enabled the kernel will keep track of bad blocks using a BBT, in addition to the OOB markers. As explained by Brian Norris the reasons for using a BBT are: "" The primary reason would be that NAND datasheets specify it these days. A better argument is that nobody guarantees that you can write a bad block marker to a worn out block; you may just get program failures. This has been acknowledged by several developers over the last several years. Additionally, you get a boot-time performance improvement if you only have to read a few pages, instead of a page or two from every block on the flash. "" Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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7d5929c1 |
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25-Aug-2014 |
Roger Quadros <rogerq@ti.com> |
mtd: nand: omap: Revert to using software ECC by default For v3.12 and prior, 1-bit Hamming code ECC via software was the default choice. Commit c66d039197e4 in v3.13 changed the behaviour to use 1-bit Hamming code via Hardware using a different ECC layout i.e. (ROM code layout) than what is used by software ECC. This ECC layout change causes NAND filesystems created in v3.12 and prior to be unusable in v3.13 and later. So revert back to using software ECC by default if an ECC scheme is not explicitely specified. This defect can be observed on the following boards during legacy boot -omap3beagle -omap3touchbook -overo -am3517crane -devkit8000 -ldp -3430sdp Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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27c9fd60 |
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19-May-2014 |
pekon gupta <pekon@ti.com> |
mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates This patch add support for BCH16_ECC in GPMC (controller) driver: - extends configuration space to include BCH16 registers - extends parsing of DT binding for selecting BCH16 ecc-scheme Signed-off-by: Pekon Gupta <pekon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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111b5a31 |
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29-Dec-2013 |
Sachin Kamat <sachin.kamat@linaro.org> |
mtd: omap2: Cleanup header files Commit 2203747c9771 ("ARM: omap: move platform_data definitions") moved the files to the current location but forgot to remove the pointer to its previous location. Clean it up. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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c66d0391 |
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24-Oct-2013 |
Pekon Gupta <pekon@ti.com> |
mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes OMAP NAND driver currently supports multiple flavours of 1-bit Hamming ecc-scheme, like: - OMAP_ECC_HAMMING_CODE_DEFAULT 1-bit hamming ecc code using software library - OMAP_ECC_HAMMING_CODE_HW 1-bit hamming ecc-code using GPMC h/w engine - OMAP_ECC_HAMMING_CODE_HW_ROMCODE 1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible to ROM code. This patch combines above multiple ecc-schemes into single implementation: - OMAP_ECC_HAM1_CODE_HW 1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible ecc-layout. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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ac65caf5 |
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24-Oct-2013 |
Pekon Gupta <pekon@ti.com> |
ARM: OMAP2+: cleaned-up DT support of various ECC schemes OMAP NAND driver support multiple ECC scheme, which can used in different flavours, depending on in-build Hardware engines present on SoC. This patch updates following in DT bindings related to sectionion of ecc-schemes - ti,elm-id: replaces elm_id (maintains backward compatibility) - ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme depends on ti,elm-id. (supported values ham1, bch4, and bch8) - maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode) Below table shows different flavours of ecc-schemes supported by OMAP devices +---------------------------------------+---------------+---------------+ | ECC scheme |ECC calculation|Error detection| +---------------------------------------+---------------+---------------+ |OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W | +---------------------------------------+---------------+---------------+ |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | |(requires CONFIG_MTD_NAND_ECC_BCH) | | | +---------------------------------------+---------------+---------------+ |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | |(requires CONFIG_MTD_NAND_OMAP_BCH && | | | | ti,elm-id in DT) | | | +---------------------------------------+---------------+---------------+ To optimize footprint of omap2-nand driver, selection of some ECC schemes also require enabling following Kconfigs, in addition to setting appropriate DT bindings - Kconfig:CONFIG_MTD_NAND_ECC_BCH error detection done in software - Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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ccf04c51 |
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14-Dec-2012 |
Daniel Mack <zonque@gmail.com> |
mtd: omap-nand: pass device_node in platform data Pass an optional device_node pointer in the platform data, which in turn will be put into a mtd_part_parser_data. This way, code that sets up the platform devices can pass along the node from DT so that the partitions can be parsed. For non-DT boards, this change has no effect. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Artem Bityutskiy <dedekind1@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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2fdf0c98 |
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04-Oct-2012 |
Afzal Mohammed <afzal@ti.com> |
ARM: OMAP2+: gpmc: nand register helper bch update Update helper function that provides gpmc-nand register details for nand driver with bch register information. Using this nand driver can be made self sufficient to handle remaining gpmc-nand operations by itself instead of relying on gpmc exported nand functions. Signed-off-by: Afzal Mohammed <afzal@ti.com>
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bc3668ea |
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28-Sep-2012 |
Afzal Mohammed <afzal@ti.com> |
ARM: OMAP2+: nand: header cleanup For common arm zImage existing nand header file in platform specific location was moved to generic platform data location, but it contained more than platform data, remove it. New local header has been created for exposing functions. Also move gpmc-nand platform data to platform header meant for nand from gpmc header file Signed-off-by: Afzal Mohammed <afzal@ti.com>
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2203747c |
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24-Aug-2012 |
Arnd Bergmann <arnd@arndb.de> |
ARM: omap: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the omap include directories Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: "Benoît Cousson" <b-cousson@ti.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Cc: Liam Girdwood <lrg@ti.com> Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Cc: Jean Pihet <j-pihet@ti.com> Cc: J Keerthy <j-keerthy@ti.com> Cc: linux-omap@vger.kernel.org
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