staging: axis-fifo: avoid parsing ignored device tree properties

Some properties were parsed from the device tree and then ignored by the
driver. Some would return an error if absent from the device tree, then
return an error if they were found because they are unsupported by the
driver.

Avoid parsing unused properties and clearly explain in the documentation
the ignored / unsupported properties.

Signed-off-by: Quentin Deslandes <quentin.deslandes@itdev.co.uk>
Link: https://lore.kernel.org/r/20191101214232.16960-2-quentin.deslandes@itdev.co.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core

This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.

See Xilinx PG080 document for IP details.

https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

The driver currently supports only store-forward mode with a 32-bit
AXI4 Lite interface. DOES NOT support:
- cut-through mode
- AXI4 (non-lite)

Signed-off-by: Jacob Feder <jacobsfeder@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>