#
36f7050b |
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12-Dec-2023 |
Nandhini Srikandan <nandhini.srikandan@intel.com> |
spi: dw: Remove Intel Thunder Bay SOC support Remove Intel Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://msgid.link/r/20231213060836.29203-2-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
349112b6 |
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23-Aug-2023 |
Li Zetao <lizetao1@huawei.com> |
spi: dw-mmio: Use helper function devm_clk_get_*() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Also, devm_clk_get_optional() and clk_prepare_enable() can now be replaced by devm_clk_get_optional_enabled(). Moreover, the lable "out_clk" no longer makes sense, rename it to "out_reset". Signed-off-by: Li Zetao <lizetao1@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230823133938.1359106-13-lizetao1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
ecd02b6d |
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16-Aug-2023 |
Yang Yingliang <yangyingliang@huawei.com> |
spi: dw-mmio: keep old name same as documentation The documentation has not use the new name(host/target), so keep the comment words same as documentation used. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230816093938.1274806-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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2ca03ecc |
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06-Aug-2023 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
spi: dw: Set default value if reg-io-width isn't specified According to the dt-bindings, the default value of reg-io-width is 4. However, the value becomes zero when reg-io-width isn't specified. Should set the actual value to dws->reg_io_width, considering it referenced. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230807001621.196776-1-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
eefc6c5c |
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28-Jul-2023 |
Yang Yingliang <yangyingliang@huawei.com> |
spi: dw: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-20-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
eee43699 |
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13-Jun-2023 |
Abe Kohandel <abe.kohandel@intel.com> |
spi: dw: Replace incorrect spi_get_chipselect with set Commit 445164e8c136 ("spi: dw: Replace spi->chip_select references with function calls") replaced direct access to spi.chip_select with spi_*_chipselect calls but incorrectly replaced a set instance with a get instance, replace the incorrect instance. Fixes: 445164e8c136 ("spi: dw: Replace spi->chip_select references with function calls") Signed-off-by: Abe Kohandel <abe.kohandel@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230613162103.569812-1-abe.kohandel@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
5b6d0b91 |
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06-Jun-2023 |
Abe Kohandel <abe.kohandel@intel.com> |
spi: dw: Remove misleading comment for Mount Evans SoC Remove a misleading comment about the DMA operations of the Intel Mount Evans SoC's SPI Controller as requested by Serge. Signed-off-by: Abe Kohandel <abe.kohandel@intel.com> Link: https://lore.kernel.org/linux-spi/20230606191333.247ucbf7h3tlooxf@mobilestation/ Fixes: 0760d5d0e9f0 ("spi: dw: Add compatible for Intel Mount Evans SoC") Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230606231844.726272-1-abe.kohandel@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
0760d5d0 |
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06-Jun-2023 |
Abe Kohandel <abe.kohandel@intel.com> |
spi: dw: Add compatible for Intel Mount Evans SoC The Intel Mount Evans SoC's Integrated Management Complex uses the SPI controller for access to a NOR SPI FLASH. However, the SoC doesn't provide a mechanism to override the native chip select signal. This driver doesn't use DMA for memory operations when a chip select override is not provided due to the native chip select timing behavior. As a result no DMA configuration is done for the controller and this configuration is not tested. The controller also has an errata where a full TX FIFO can result in data corruption. The suggested workaround is to never completely fill the FIFO. The TX FIFO has a size of 32 so the fifo_len is set to 31. Signed-off-by: Abe Kohandel <abe.kohandel@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230606145402.474866-2-abe.kohandel@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
445164e8 |
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15-May-2023 |
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> |
spi: dw: Replace spi->chip_select references with function calls New set/get APIs for accessing spi->chip_select were introduced by 'commit 9e264f3f85a5 ("spi: Replace all spi->chip_select and spi->cs_gpiod references with function call")', but the 'commit 2c8606040a80 ("spi: dw: Add support for AMD Pensando Elba SoC")' uses the old interface by directly accessing spi->chip_select. So, replace all spi->chip_select references in the driver with new get/set APIs. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com Acked-by: Serge Semin <fancer.lancer@gmail.com Link: https://lore.kernel.org/r/20230515130343.63770-1-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org
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#
2c860604 |
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10-Apr-2023 |
Brad Larson <blarson@amd.com> |
spi: dw: Add support for AMD Pensando Elba SoC The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson <blarson@amd.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230410184526.15990-11-blarson@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
9e264f3f |
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10-Mar-2023 |
Amit Kumar Mahapatra via Alsa-devel <alsa-devel@alsa-project.org> |
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
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#
f74abea2 |
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03-Mar-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
spi: dw-mmio: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230303172041.2103336-23-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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#
dc4e6d9f |
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12-Jul-2022 |
Nandhini Srikandan <nandhini.srikandan@intel.com> |
spi: dw: Add support for Intel Thunder Bay SPI controller Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
2b8a47e0 |
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15-Nov-2021 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Replace DWC_HSSI capability with IP-core version checker Since there is a common IP-core and component versions interface available we can use it to differentiate the DW HSSI device features in the code. Let's remove the corresponding DWC_HSSI capability flag then and use the dw_spi_ip_is() macro instead. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20211115181917.7521-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
725b0e3e |
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15-Nov-2021 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Put the driver entities naming in order Mostly due to a long driver history it's methods and macro names look a bit messy. In particularly that concerns the code their prefixes. A biggest part of the driver functions and macros have got the dw_spi/DW_SPI prefixes. But there are some entities which have been just "spi_/SPI_"-prefixed. Especially that concerns the CSR and their fields macro definitions. It makes the code harder to comprehend since such methods and macros can be easily confused with the global SPI-subsystem exports. In this case the only possible way to more or less quickly distinguish one naming space from another is either by context or by the argument type, which most of the times isn't that easy anyway. In addition to that a new DW SSI IP-core support has been added in the framework of commit e539f435cb9c ("spi: dw: Add support for DesignWare DWC_ssi"), which introduced a new set or macro-prefixes to describe CTRLR0-specific fields and worsen the situation. Finally there are methods with no DW SPI driver-reference prefix at all, that make the code reading even harder. So in order to ease the driver hacking let's bring the code naming to a common base: 1) Each method is supposed to have "dw_spi_" prefix so to be easily distinguished from the kernel API, e.g. SPI-subsystem methods and macros. (Exception is the local implementation of the readl/writel methods since being just the regspace accessors.) 2) Each generically used macro should have DW_SPI_-prefix thus being easily comprehended as the local driver definition. 3) DW APB SSI and DW SSI specific macros should have prefixes as DW_PSSI_ and DW_HSSI_ respectively so referring to the system buses they support (APB and AHB similarly to the DT clocks naming like pclk, hclk). Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20211115181917.7521-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
a62bacba |
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15-Nov-2021 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Add a symbols namespace for the core module The exported from the DW SPI driver core/DMA symbols are only used by the spi-dw-{mmio,pci,bt1}.o objects. Add these symbols to a separate namespace then and make sure the depended modules have it imported. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20211115181917.7521-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
db56d030 |
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10-May-2021 |
Jay Fang <f.fangjian@huawei.com> |
spi: delete repeated words in comments Drop repeated words in spi-bcm2835aux.c {are} Drop repeated words in spi-dw-mmio.c {the} Drop repeated words in spi-geni-qcom.c {our} Drop repeated words in spi-pl022.c {on} Drop repeated words in spi-ppc4xx.c {the} Signed-off-by: Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1620629903-15493-4-git-send-email-f.fangjian@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
b0dfd948 |
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05-Dec-2020 |
Damien Le Moal <damien.lemoal@wdc.com> |
spi: dw: Add support for the Canaan K210 SoC SPI The Canaan Kendryte K210 RISC-V SoC includes a DW apb_ssi v4 controller which is documented to have a 32 words deep TX and RX FIFO. The FIFO length detection in spi_hw_init() correctly detects this value. However, when the controller RX FIFO is filled up to 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. This likely due to a hardware bug which can be avoided by force setting the fifo_len field of struct dw_spi to 31. Define the dw_spi_canaan_k210_init() function to force set fifo_len to 31 when the device node compatible string is "canaan,k210-spi". Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20201206011817.11700-4-damien.lemoal@wdc.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
d6bbd119 |
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07-Oct-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Add DWC SSI capability Currently DWC SSI core is supported by means of setting up the core-specific update_cr0() callback. It isn't suitable for multiple reasons. First of all having exported several methods doing the same thing but for different chips makes the code harder to maintain. Secondly the spi-dw-core driver exports the methods, then the spi-dw-mmio driver sets the private data callback with one of them so to be called by the core driver again. That makes the code logic too complicated. Thirdly using callbacks for just updating the CR0 register is problematic, since in case if the register needed to be updated from different parts of the code, we'd have to create another callback (for instance the SPI device-specific parameters don't need to be calculated each time the SPI transfer is submitted, so it's better to pre-calculate the CR0 data at the SPI-device setup stage). So keeping all the above in mind let's discard the update_cr0() callbacks, define a generic and static dw_spi_update_cr0() method and create the DW_SPI_CAP_DWC_SSI capability, which when enabled would activate the alternative CR0 register layout. While at it add the comments to the code path of the normal DW APB SSI controller setup to make the dw_spi_update_cr0() method looking coherent. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201007235511.4935-3-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
ffb7ca54 |
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20-Sep-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Add KeemBay Master capability In a further commit we'll have to get rid of the update_cr0() callback and define a DW SSI capability instead. Since Keem Bay master/slave functionality is controller by the CTRL0 register bitfield, we need to first move the master mode selection into the internal corresponding update_cr0 method, which would be activated by means of the dedicated DW_SPI_CAP_KEEMBAY_MST capability setup. Note this will be also useful if the driver will be ever altered to support the DW SPI slave interface. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20200920112914.26501-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
cc760f31 |
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20-Sep-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Convert CS-override to DW SPI capabilities There are several vendor-specific versions of the DW SPI controllers, each of which may have some peculiarities with respect to the original IP-core. Seeing it has already caused adding flags and a callback into the DW SPI private data, let's introduce a generic capabilities interface to tune the generic DW SPI controller driver up in accordance with the particular controller specifics. It's done by converting a simple Alpine-specific CS-override capability into the DW SPI controller capability activated by setting the DW_SPI_CAP_CS_OVERRIDE flag. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20200920112914.26501-10-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
53a09635 |
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24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
spi: dw: Add Microchip Sparx5 support This adds SPI support for the Sparx5 SoC, which is using the MMIO Designware SPI controller. The Sparx5 differs from the Ocelot version in these areas: * The CS override is controlled by a new set of registers for this purpose. * The Sparx5 SPI controller has the RX sample delay register, and it must be configured for the (SPI NAND) device on SPI2. * The Sparx5 SPI controller has 2 different SPI bus interfaces on the same controller (don't ask...). The "spi-mux" driver should be used in conjunction with the SPI driver to select the appropriate bus. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-3-lars.povlsen@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
7830c0ef |
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29-May-2020 |
Dinh Nguyen <dinguyen@kernel.org> |
spi: dw: add reset control Add mechanism to get the reset control and deassert it in order to bring the IP out of reset. Signed-off-by: Liang Jin J <liang.j.jin@ericsson.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200529155806.16758-1-dinguyen@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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#
0fdad596 |
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29-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Add DMA support to the DW SPI MMIO driver Since the common code in the spi-dw-dma.c driver is ready to be used by the MMIO driver and now provides a method to generically (on any DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers, we can use it and a set of the common DW SPI DMA callbacks to enable DMA at least for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a" devices. Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200529131205.31838-15-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
77810d48 |
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15-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Initialize paddr in DW SPI MMIO private data This field is used only for the DW SPI DMA code initialization, that's why there were no problems with it being uninitialized in Dw SPI MMIO driver. Since in a further patch we are going to introduce the DW SPI DMA support in the MMIO version of the driver, lets set the field with the physical address of the DW SPI controller registers region. Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200515104758.6934-12-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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#
afb7f565 |
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12-May-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw: Drop duplicate error message when remap resource devm_platform_ioremap_resource() will issue a message in the error case. Thus, no need to duplicate in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200512110315.58845-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
4dd227a5 |
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08-May-2020 |
Jay Fang <f.fangjian@huawei.com> |
spi: dw-mmio: Do not add acpi modalias when CONFIG_ACPI is not enabled Reduce unnecessary static memory allocation when CONFIG_ACPI is not enabled. Signed-off-by: Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1588991392-24219-1-git-send-email-f.fangjian@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
0c2ce3fe |
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06-May-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw: Move interrupt.h to spi-dw.h who is user of it The actual user of interrupt.h is spi-dw.h and not bus drivers. Move header there. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-3-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
f4237791 |
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05-May-2020 |
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> |
spi: dw: Add support for Intel Keem Bay SPI Add support for Intel Keem Bay SPI controller, which uses DesignWare DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to configure the device as a master or as a slave serial peripheral. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-6-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
e539f435 |
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05-May-2020 |
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> |
spi: dw: Add support for DesignWare DWC_ssi This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is the enhanced version of DW_apb_ssi, which is currently supported by this driver. Their registers are same, but the bit fields of register CTRLR0 are different. DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave device. Register offset DW_ssi DW_apb_ssi CTRLR0 0x00 0x00 CTRLR1 0x04 0x04 SSIENR 0x08 0x08 MWCR 0x0c 0x0c SER 0x10 0x10 BAUDR 0x14 0x14 TXFTLR 0x18 0x18 RXFTLR 0x1c 0x1c TXFLR 0x20 0x20 RXFLR 0x24 0x24 SR 0x28 0x28 IMR 0x2c 0x2c ISR 0x30 0x30 RISR 0x34 0x34 TXOICR 0x38 0x38 RXOICR 0x3c 0x3c RXUICR 0x40 0x40 MSTICR 0x44 0x44 ICR 0x48 0x48 DMACR 0x4c 0x4c DMATDLR 0x50 0x50 DMARDLR 0x54 0x54 IDR 0x58 0x58 SSI_VERSION_ID 0x5c 0x5c DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4 RX_SAMPLE_DLY 0xf0 0xf0 SPI_CTRLR0 0xf4 0xf4 TXD_DRIVE_EDGE 0xf8 0xf8 XIP_MODE_BITS 0xfc RSVD Register configuration - CTRLR0 DW_ssi DW_apb_ssi SPI_HYPERBUS_EN bit[24] NONE SPI_FRF bit[23:22] bit[22:21] DFS_32 NONE bit[20:16] CFS bit[19:16] bit[15:12] SSTE bit[14] bit[24] SRL bit[13] bit[11] SLV_OE bit[12] bit[10] TMOD bit[11:10] bit[9:8] SCPOL | SPHA bit[9:8] bit[7:6] FRF bit[7:6] bit[5:4] DFS bit[4:0] bit[3:0] The documents used are [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a). [2] DWC_ssi_databook.pdf version 1.01a. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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c4eadee2 |
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05-May-2020 |
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> |
spi: dw: Add update_cr0() callback to update CTRLR0 This patch adds update_cr0() callback, in struct dw_spi. Existing code that configure register CTRLR0 is moved into a new function, dw_spi_update_cr0(), and this will be the default. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200505130618.554-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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b9fc2d20 |
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18-Oct-2019 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
spi: dw: Move runtime PM enable/disable from common to platform driver part After commit 1e6959832510 ("spi: dw: Add basic runtime PM support") there is following warning from PCI enumerated DesignWare SPI controller during probe: dw_spi_pci 0000:00:13.0: Unbalanced pm_runtime_enable! Runtime PM is already enabled for PCI devices by the PCI core and doing it again in common DW SPI code leads to unbalanced enable calls. Fix this by moving the runtime PM enable/disable calls to the platform driver part of the driver. Cc: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20191018132131.31608-1-jarkko.nikula@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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3ade3a37 |
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18-Sep-2019 |
Phil Edworthy <phil.edworthy@renesas.com> |
spi: dw: Add compatible string for Renesas RZ/N1 SPI Controller The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI, but has additional registers for software CS control and DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. The CS registers are not needed as Linux can use gpios for the CS signals. Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/1568793876-9009-5-git-send-email-gareth.williams.jx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
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5cc6fdcc |
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04-Sep-2019 |
YueHaibing <yuehaibing@huawei.com> |
spi: dw-mmio: use devm_platform_ioremap_resource() to simplify code Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190904135918.25352-13-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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6b8ac10e |
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30-Jul-2019 |
Stephen Boyd <swboyd@chromium.org> |
spi: Remove dev_err() usage after platform_get_irq() We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
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3da9834d |
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10-Jul-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw-mmio: Clock should be shut when error occurs When optional clock requesting fails, the main clock is still up and running, we should shut it down in such caee. Fixes: 560ee7e91009 ("spi: dw: Add support for an optional interface clock") Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Gareth Williams <gareth.williams.jx@renesas.com> Link: https://lore.kernel.org/r/20190710114243.30101-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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05210502 |
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10-Jul-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw-mmio: Use devm_platform_ioremap_resource() Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190710114230.30047-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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75a6faf6 |
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01-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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560ee7e9 |
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19-Mar-2019 |
Phil Edworthy <phil.edworthy@renesas.com> |
spi: dw: Add support for an optional interface clock The Synopsys SSI Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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9400c41e |
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07-Jan-2019 |
Linus Walleij <linus.walleij@linaro.org> |
spi: dw: Convert to use CS GPIO descriptors This converts the DesignWare (dw) SPI master driver to use GPIO descriptors for chip select handling. This driver has a duplicate DT parser in addition to the one in the core, sets up the line as non-asserted and relies on the core to drive the GPIOs. It is a pretty straight-forward conversion. Cc: Talel Shenhar <talel@amazon.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Linuxarm <linuxarm@huawei.com> Tested-by: Jay Fang <f.fangjian@huawei.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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32215a6c |
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02-Dec-2018 |
Jay Fang <f.fangjian@huawei.com> |
spi: dw-mmio: add ACPI support The Hisilicon Hip08 platform, that uses ACPI, has this controller. Let's add ACPI support for DW SPI MMIO-based host. The ACPI ID used is "HISI0173" for the Designware SPI controller of Hisilicon Hip08 platform. Signed-off-by: Jay Fang <f.fangjian@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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f2d70479 |
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11-Oct-2018 |
Talel Shenhar <talel@amazon.com> |
dw: spi: add support for Amazon's Alpine spi controller Add support for a new devicetree compatible string called 'amazon,alpine-apb-ssi', which is necessary for the Amazon Alpine spi controller. 'amazon,alpine-dw-apb-ssi' is used in the dw spi driver if specified in the devicetree. Otherwise, fall back to driver default behavior, i.e. original dw IP hw driver behavior. Signed-off-by: Talel Shenhar <talel@amazon.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Mark Brown <broonie@kernel.org>
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c1d8b082 |
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31-Aug-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
spi: dw-mmio: avoid hardcoded field mask Define a mask for the IF_SI_OWNER field. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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be17ee0d |
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29-Aug-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
spi: dw-mmio: add MSCC Jaguar2 support Unfortunately, the Jaguar2 CPU_SYSTEM_CTRL register set has a different layout than the Ocelot one. Handle that while keeping most of the code common. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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c2c25cc3 |
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27-Jul-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
spi: dw-mmio: add MSCC Ocelot support Because the SPI controller deasserts the chip select when the TX fifo is empty (which may happen in the middle of a transfer), the CS should be handled by linux. Unfortunately, some or all of the first four chip selects are not muxable as GPIOs, depending on the SoC. There is a way to bitbang those pins by using the SPI boot controller so use it to set the chip selects. At init time, it is also necessary to give control of the SPI interface to the Designware IP. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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400c18e3 |
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18-Apr-2017 |
Marek Vasut <marex@denx.de> |
spi: dw: Disable clock after unregistering the host The dw_mmio driver disables the block clock before unregistering the host. The code unregistering the host may access the SPI block registers. If register access happens with block clock disabled, this may lead to a bus hang. Disable the clock after unregistering the host to prevent such situation. This bug was observed on Altera Cyclone V SoC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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2f6fdefb |
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05-Feb-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw-mmio: remove message which is handled by core devm_ioremap_resource() validates its parameters and issues an error message if needed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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9899995e |
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14-Oct-2015 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
spi: dw-mmio: convert to unified device property API Convert the driver to use unfied device property API instead of OF one. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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c4fe57f7 |
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18-Aug-2015 |
Michael van der Westhuizen <michael@smart-africa.com> |
spi: dw: Allow interface drivers to limit data I/O to word sizes The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Both the core and the MMIO interface driver default to the current 32bit behaviour. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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14ac00e0 |
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20-Oct-2014 |
Wolfram Sang <wsa@kernel.org> |
spi: drop owner assignment from platform_drivers A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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22dae17e |
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13-Jun-2014 |
Steffen Trumtrar <s.trumtrar@pengutronix.de> |
spi: dw-mmio: add devicetree support Allow probing the dw-mmio from devicetree. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>
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d9c73bb8 |
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30-Jan-2014 |
Baruch Siach <baruch@tkos.co.il> |
spi: dw: add support for gpio controlled chip select Also, use this opportunity to let spi_chip_sel() handle chip-select deactivation as well. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
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2418991e |
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26-Jan-2014 |
Baruch Siach <baruch@tkos.co.il> |
spi: dw-mmio: allow multiple instances Use the platform_device id to uniquely identify each SPI master instance. Cc: Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
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020fe3fe |
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30-Dec-2013 |
Baruch Siach <baruch@tkos.co.il> |
spi: dw-mmio: prepare the clock before enabling This is required for common clock support. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
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04f421e7 |
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30-Dec-2013 |
Baruch Siach <baruch@tkos.co.il> |
spi: dw: use managed resources Migrate mmio code and core driver to managed resources to reduce boilerplate error handling code. Also, handle clk_enable() failure while at it, and drop unused dw_spi iolen field. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Mark Brown <broonie@linaro.org>
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1e0d191f |
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02-Sep-2013 |
Julia Lawall <Julia.Lawall@lip6.fr> |
spi: designware: delete premature free_irq Free_irq is not needed if there has been no request_irq. Free_irq is removed from both the probe and remove functions. The correct request_irq and free_irq appear to be in the add_host and remove_host functions in spi-dw.c. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e; @@ *e = platform_get_irq(...); ... when != request_irq(e,...) *free_irq(e,...) // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Mark Brown <broonie@linaro.org>
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89e87730 |
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03-May-2013 |
Jingoo Han <jg1.han@samsung.com> |
spi: remove unnecessary platform_set_drvdata() The driver core clears the driver data to NULL after device_release or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d (device-core: Ensure drvdata = NULL when no driver is bound). Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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fd4a319b |
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07-Dec-2012 |
Grant Likely <grant.likely@secretlab.ca> |
spi: Remove HOTPLUG section attributes CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Bill Pemberton has done most of the legwork on this series. I've used his script to purge the attributes from the drivers/gpio tree. Reported-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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d7614de4 |
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03-Jul-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
spi: Add module.h to implicit users in drivers/spi We are clipping down the presence of module.h, since it was everywhere. If you really need it, you better call it out, as per this changeset. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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940ab889 |
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05-Oct-2011 |
Grant Likely <grant.likely@secretlab.ca> |
drivercore: Add helper macro for platform_driver boilerplate For simple modules that contain a single platform_driver without any additional setup code then ends up being a block of duplicated boilerplate. This patch adds a new macro, module_platform_driver(), which replaces the module_init()/module_exit() registrations with template functions. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Reviewed-by: Magnus Damm <magnus.damm@gmail.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
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ca632f55 |
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06-Jun-2011 |
Grant Likely <grant.likely@secretlab.ca> |
spi: reorganize drivers Sort the SPI makefile and enforce the naming convention spi_*.c for spi drivers. This change also rolls the contents of atmel_spi.h into the .c file since there is only one user of that particular include file. v2: - Use 'spi-' prefix instead of 'spi_' to match what seems to be be the predominant pattern for subsystem prefixes. - Clean up filenames in Kconfig and header comment blocks Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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