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8402074f |
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16-Oct-2023 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Add support for Tegra241 Add support for Tegra241 which use ACPI boot. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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f28cd697 |
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12-Sep-2023 |
Ulf Hansson <ulf.hansson@linaro.org> |
pmdomain: tegra: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: <linux-tegra@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6d8257ca |
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05-Jun-2023 |
Prathamesh Shete <pshete@nvidia.com> |
pinctrl: tegra: Add Tegra234 pinmux driver This change adds support for the two pin controllers found on Tegra234. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230605154230.2910847-3-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ba4b4d02 |
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15-Dec-2022 |
Arnd Bergmann <arnd@arndb.de> |
soc: tegra: fix CPU_BIG_ENDIAN dependencies My previous patch to prevent BPMP from being enabled on big endian kernels caused a build regression: WARNING: unmet direct dependencies detected for TEGRA_BPMP Depends on [n]: ARCH_TEGRA [=y] && TEGRA_HSP_MBOX [=y] && TEGRA_IVC [=y] && !CPU_BIG_ENDIAN [=y] Selected by [y]: - ARCH_TEGRA_186_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_194_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_234_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] Add even more such dependencies for the SoC types that use the BPMP driver. Fixes: 4ddb1bf1a837 ("tegra: mark BPMP driver as little-endian only") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221215165336.1781080-1-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
28dbe823 |
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02-Oct-2022 |
Petlozu Pravareshwar <petlozup@nvidia.com> |
soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY Tegra PMC driver depends on IRQ domain hierarchy support, hence select the IRQ_DOMAIN_HIERARCHY config for SOC_TEGRA_PMC. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
22541828 |
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22-Sep-2020 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA The DMA subsystem could be entirely disabled in Kconfig and then the TEGRA20_APB_DMA option isn't available too. Hence kernel configuration fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable dependency. The FUSE driver isn't a critical driver and currently it only provides NVMEM interface to userspace which isn't known to be widely used, and thus, it's fine if FUSE driver fails to load. Let's remove the erroneous Kconfig dependency and let the FUSE driver to fail the probing if DMA is unavailable. Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20") Reported-by: Necip Fazil Yildiran <fazilyildiran@gmail.com> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301 Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
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#
fc2f151d |
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11-May-2022 |
Sumit Gupta <sumitg@nvidia.com> |
soc/tegra: cbb: Add driver for Tegra234 CBB 2.0 Adding driver to handle errors from CBB version 2.0 which is used in Tegra234 SoC. The driver prints debug information about failed transaction on receiving interrupt from the error notifier. The error notifier collates the interrupts from various error monitor blocks and presents a single interrupt to the SoC interrupt controller. For timeout errors, the driver also does the lookup to find timed out clients and prints their client ID. Drivers for hardware that needs to be reset on timeout will have to call BPMP from the client IP's driver. BPMP firmware will also clear the timeout bit after resetting the IP so that next transactions are send to them after reset. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b7134422 |
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11-May-2022 |
Sumit Gupta <sumitg@nvidia.com> |
soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
9767d1be |
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04-May-2022 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: pmc: Select REGMAP Commit 9d5e7c3e36eb ("soc/tegra: pmc: Provide USB sleepwalk register map") introduced a dependency on the regmap infrastructure, so select the corresponding Kconfig entry. This avoids failures in random builds that may otherwise end up having SOC_TEGRA_PMC enabled but not REGMAP. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
a4282f66 |
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21-Jul-2021 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: Make regulator couplers depend on CONFIG_REGULATOR The regulator coupler drivers now use regulator-driver API function that isn't available during compile-testing. Make regulator coupler drivers dependent on CONFIG_REGULATOR in Kconfig. Fixes: 03978d42ed0d ("soc/tegra: regulators: Bump voltages on system reboot") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
f880ee9e |
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31-May-2021 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: pmc: Add core power domain NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a level which satisfies all devices within the power domain. Add support for the core power domain which controls voltage state of the domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs. The PMC powergate domains now are sub-domains of the core domain, this requires device-tree updating, older DTBs are unaffected and will continue to work as before. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> [treding@nvidia.com: squash lockdep class removal patch] Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
63944891 |
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16-Sep-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Initial Tegra234 VDK support The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
5098e2b9 |
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18-Mar-2020 |
Corentin Labbe <clabbe@baylibre.com> |
soc/tegra: pmc: Select GENERIC_PINCONF I have hit the following build error: armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o: in function `pinconf_generic_dt_node_to_map_pin': pmc.c:(.text+0x500): undefined reference to `pinconf_generic_dt_node_to_map' armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o:(.rodata+0x1f88): undefined reference to `pinconf_generic_dt_free_map' So SOC_TEGRA_PMC should select GENERIC_PINCONF. Fixes: 4a37f11c8f57 ("soc/tegra: pmc: Implement pad configuration via pinctrl") Cc: stable <stable@vger.kernel.org> Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
19d41e5e |
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29-Dec-2019 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: fuse: Add APB DMA dependency for Tegra20 Tegra20 FUSE driver depends on DMA channel presence, otherwise it fails to probe. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
78380743 |
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25-Jul-2019 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: regulators: Add regulators coupler for Tegra30 Add regulators coupler for Tegra30 SoCs that performs voltage balancing of a coupled regulators and thus provides voltage scaling functionality. There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The coupled regulator voltages shall be in a range of 300mV from each other and CORE voltage shall be higher than the CPU by N mV, where N depends on the CPU voltage. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
496747e7 |
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25-Jul-2019 |
Dmitry Osipenko <digetx@gmail.com> |
soc/tegra: regulators: Add regulators coupler for Tegra20 Add regulators coupler for Tegra20 SoCs that performs voltage balancing of a coupled regulators and thus provides voltage scaling functionality. There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU. The CORE and RTC voltages shall be in range of 170mV from each other and they both shall be higher than the CPU voltage by at least 120mV. This sounds like it could be handle by a generic voltage balancer, but the CORE voltage scaling isn't implemented in any of the upstream drivers yet. It will take quite some time and effort to hook up voltage scaling for all of the drivers, hence we will use a custom coupler that will manage the CPU voltage scaling for the starter. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
7ac13f6d |
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16-May-2019 |
Krishna Yarlagadda <kyarlagadda@nvidia.com> |
soc/tegra: Select pinctrl for Tegra194 Select PINCTRL_TEGRA194 by default for Tegra194 SoC needed for dynamically controlling PCIe pins. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
ec8f24b7 |
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19-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
f40f4fc9 |
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21-Feb-2019 |
Joseph Lo <josephl@nvidia.com> |
soc/tegra: default select TEGRA_TIMER for Tegra210 The tegra timer is necessary for Tegra210 to support CPU idle power-down state. So select it by default. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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6f9ed07f |
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20-Feb-2018 |
Mikko Perttunen <mperttunen@nvidia.com> |
soc/tegra: Add Tegra194 SoC configuration option Add the configuration option to enable support for the Tegra194 system- on-chip. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
c641ec6e |
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29-Aug-2017 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: pmc: Consolidate Tegra186 support Move Tegra186 support to the consolidated PMC driver to reduce some of the duplication and also gain I/O pad functionality on the new SoC as a side-effect. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
27a0342a |
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17-Aug-2017 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: Register SoC device Move this code from arch/arm/mach-tegra and make it common among 32-bit and 64-bit Tegra SoCs. This is slightly complicated by the fact that on 32-bit Tegra, the SoC device is used as the parent for all devices that are instantiated from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
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e7149a7a |
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29-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: bpmp: Implement generic PM domains The BPMP firmware, found on Tegra186 and later, provides an ABI that can be used to enable and disable power to several power partitions in Tegra SoCs. The ABI allows for enumeration of the available power partitions, so the driver can be reused on future generations, provided the BPMP ABI remains stable. Based on work by Stefan Kristiansson <stefank@nvidia.com> and Mikko Perttunen <mperttunen@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
1fd09e5d |
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28-Mar-2017 |
Jon Hunter <jonathanh@nvidia.com> |
soc/tegra: Add initial flowctrl support for Tegra132/210 Tegra132 and Tegra210 support the flowctrl module and so add initial support for these devices. Please note that Tegra186 does not support the flowctrl module, so update the initialisation function such that we do not fall back and attempt to map the 'hardcoded' address range for Tegra186. Furthermore 64-bit Tegra devices have always had the flowctrl node defined in their device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
7e10cf74 |
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28-Mar-2017 |
Jon Hunter <jonathanh@nvidia.com> |
soc/tegra: Move Tegra flowctrl driver The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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5e7d4c65 |
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23-Feb-2017 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: Implement Tegra186 PMC support The power management controller on Tegra186 has changed in backwards- incompatible ways with respect to earlier generations. This implements a new driver that supports inversion of the PMU interrupt as well as the "recovery", "bootloader" and "forced-recovery" reboot commands. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
25a06442 |
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05-Jul-2016 |
Joseph Lo <josephl@nvidia.com> |
soc/tegra: Add Tegra186 support The Tegra186 features a combination of Denver and Cortex-A57 CPU cores and a GPU based on the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU used for audio processing, hardware video encoders and decoders with multi-format support, ISP for image capture processing and BPMP for power management. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
955d809b |
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23-Jan-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select These two are both ARMv7 SoCs. They need not explicitly select ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7. Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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a262e87f |
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23-Nov-2015 |
Arnd Bergmann <arnd@arndb.de> |
ARM: tegra: select USB_ULPI from EHCI rather than platform For historic reasons, the tegra platform selects USB_ULPI from architecture code, but that hasn't really made sense for a long time, as the only user of that code is the Tegra EHCI driver that has its own Kconfig symbol. This removes the 'select' statements from mach-tegra and drivers/soc/tegra and adds them with the device driver that actually needs them. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
95445952 |
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15-Nov-2015 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: Add Tegra210 support Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a Kconfig option for Tegra210 to allow SoC-specific support to be enabled for this new generation. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
099a6644 |
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09-Sep-2015 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: Provide per-SoC Kconfig symbols Move per-SoC generation Kconfig symbols to drivers/soc/tegra/Kconfig to gather them all in a single place. This directory is a natural location for these options since it already contains the drivers that are shared across 32-bit and 64-bit ARM architectures. Signed-off-by: Thierry Reding <treding@nvidia.com>
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