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873e65bc |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 167 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 83 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.021731668@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c56f5f1d |
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27-Dec-2015 |
Wilfried Weissmann <Wilfried.Weissmann@gmx.at> |
mvsas: Add SGPIO support to Marvell 94xx Add SGPIO support to Marvell 94xx. Signed-off-by: Wilfried Weissmann <Wilfried.Weissmann@gmx.at> Reviewed-by: James Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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8902b107 |
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08-May-2014 |
Chen Gang <gang.chen.5i5j@gmail.com> |
drivers: scsi: mvsas: fix compiling issue by adding 'MVS_' for "enum pci_interrupt_cause" The direct cause is IRQ_SPI is already defined as a macro in unicore32 architecture (also, blackfin and mips architectures define it). The related error (unicore32 with allmodconfig) CC [M] drivers/scsi/mvsas/mv_94xx.o In file included from drivers/scsi/mvsas/mv_94xx.c:27: drivers/scsi/mvsas/mv_94xx.h:176: error: expected identifier before numeric constant And IRQ_SAS_A and IRQ_SAS_B are used as 'u32' (although "enum pci_interrupt_cause" is not used directly, now). All together, need add 'MVS_' for "enum pci_interrupt_cause". Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Xuetao Guan <gxt@mprc.pku.edu.cn> Signed-off-by: Xuetao Guan <gxt@mprc.pku.edu.cn>
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beecadea |
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16-Nov-2012 |
Xi Wang <xi.wang@gmail.com> |
[SCSI] mvsas: fix undefined bit shift The macro bit(n) is defined as ((u32)1 << n), and thus it doesn't work with n >= 32, such as in mvs_94xx_assign_reg_set(): if (i >= 32) { mvi->sata_reg_set |= bit(i); ... } The shift ((u32)1 << n) with n >= 32 also leads to undefined behavior. The result varies depending on the architecture. This patch changes bit(n) to do a 64-bit shift. It also simplifies mv_ffc64() using __ffs64(), since invoking ffz() with ~0 is undefined. Signed-off-by: Xi Wang <xi.wang@gmail.com> Acked-by: Xiangliang Yu <yuxiangl@marvell.com> Cc: stable@vger.kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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e144f7ef |
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24-May-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: update comments Remove obsolete comments and add new comments Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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84fbd0ce |
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24-May-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: misc improvements Change code to match HBA datasheet. Change code to make it readable. Add support big endian for mvs_prd_imt. Add cpu_to_le32 and cpu_to_le64 to use on addr. Add scan_finished for structure mvs_prv_info. Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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a4632aae |
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24-May-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: Add new macros and functions Add new macros: MVS_SOFT_RESET, MVS_HARD_RESET, MVS_PHY_TUNE, MVS_COMMAND_ACTIVE, EXP_BRCT_CHG, MVS_MAX_SG Add new member sg_width in struct mvs_chip_info Use macros rather than magic number Add new functions: mvs_fill_ssp_resp_iu, mvs_set_sense, mvs_94xx_clear_srs_irq, mvs_94xx_phy_set_link_rate Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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b89e8f53 |
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24-May-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: Remove unused macros, variables and functions Remove unused macros: VSR_PHY_VS0, VSR_PHY_VS1, MVS_SLOTS, MVS_CAN_QUEUE, MVS_MSI, SG_MX, _MV_DUMP, MV_DISABLE_NCQ Remove unused variables for mvs_info: irq, exp_req, cmd_size Remove unused functions: mvs_get_sas_addr, mvs_hexdump, mvs_hba_sb_dump, mvs_hab_memory_dump, mvs_hba_cq_dump Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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f1f82a91 |
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24-May-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: add support for 94xx phy tuning and multiple revisions Add 94xx phy tuning to aid manufacturing. Add support for 94xx multiple revisions: A0, B0, C0, C1, C2. Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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0b15fb1f |
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26-Apr-2011 |
Xiangliang Yu <yuxiangl@marvell.com> |
[SCSI] mvsas: add support for Task collector mode and fixed relative bugs 1. Add support for Task collector mode. 2. Fixed relative collector mode bug: - I/O failed when disks is on two ports - system hang when hotplug disk - system hang when unplug disk during run IO 3. Unlock ap->lock within .lldd_execute_task for direct mode to improve performance Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
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20b09c29 |
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08-May-2009 |
Andy Yan <ayan@marvell.com> |
[SCSI] mvsas: add support for 94xx; layout change; bug fixes This version contains following main changes - Switch to new layout to support more types of ASIC. - SSP TMF supported and related Error Handing enhanced. - Support flash feature with delay 2*HZ when PHY changed. - Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2 88SE64xx chips but any different register description. - Support SPI flash for HBA-related configuration info. - Other patch enhanced from kernel side such as increasing PHY type [jejb: fold back in DMA_BIT_MASK changes] Signed-off-by: Ying Chu <jasonchu@marvell.com> Signed-off-by: Andy Yan <ayan@marvell.com> Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
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