platform/mellanox: Add support for new SN2201 system

The SN2201 is a highly integrated for one rack unit system with
L3 management switches. It has 48 x 1Gbps RJ45 + 4 x 100G QSFP28
ports in a compact 1RU form factor. The system also including a
serial port (RS-232 interface), an OOB port (1G/100M MDI interface)
and USB ports for management functions.

The processor used on SN2201 is Intel Atom®Processor C Series,
C3338R which is one of the Denverton product families.

System equipped with Nvidia®Spectrum-1 32x100GbE Ethernet switch.

Features:
- 48 ports RJ45 support 10/100/1000M speed.
- Support 4 QSFP28 ports with 10/25/40/50/100G.
- A USB port is available on SN2201. This port is used for image and File
Management purposes - backing up and restoring images and config files
- Provides flow control mechanism to ensure zero packet loss.
Uses backpressure for half-duplex operation and IEEE802.3x
for full duplex operation.
- Cut-through and Store-and-Forward free switching mechanism.
By default the mode is cut-through.
- Standard 1U chassis height.
- 19" rack mountable.
- Extensive system LED and per port LEDs.
- Redundant power supply.
- 2 x AC Power Supply (one PSU is default, second PSU is optional).

Signed-off-by: Michael Shych <michaelsh@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Link: https://lore.kernel.org/r/20220430115809.54565-3-michaelsh@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices

Provide support for the Nvidia MSN4800-XX line cards for MSN4800
Ethernet modular switch system, providing a high performance switching
solution for Enterprise Data Centers (EDC) for building Ethernet based
clusters, High-Performance Computing (HPC) and embedded environments.
Initial version provides support for line card type MSN4800-C16. This
type of line card is equipped with:
- Lattice CPLD device, used for system and ports control.
- four Nvidia gearbox devices, used for port splitting.
- FPGA device, used for gearboxes management.
- 16x100G QSFP28 ports.
- hotpswap controllers, voltage regulators, analog-to-digital
convertors, nvram devices.
- status LED.

During initialization driver creates:
- line card's I2C tree through "i2c-mux-mlxcpd" driver.
- line card's LED objects through "leds-mlxreg" driver.
- line card's CPLD register space input / output "hwmon" attributes for
line control and monitoring through "mlxreg-io" driver. These
attributes provide CPLD and FPAG versioning, control for upgradable
components burning, NVRAM devices write protection, line card
revision, line card power consuming, line card reset cause
indication, etcetera.

Lattice CPLD device and nvram devices are feeding from auxiliary power
domain and accessible, when line card is powered off. These devices
are connected by line card driver probing routine, invoked after line
card security verification is done by hardware and event lc#n_verified
is received for line card located in slot #n.

Gearboxes, FPGA, hotpswap controllers, voltage regulators,
analog-to-digital convertors are feeding from main power domain. These
devices are connected after power good event "lc#n_powered" is received
for line card located in slot #n.

The driver 'mlxreg-lc' is driven by 'mlxreg-hotplug' driver following
relevant "hotplug" events.

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20211002093238.3771419-8-vadimp@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

platform/mellanox: mlxbf-pmc: Add Mellanox BlueField PMC driver

The performance modules in BlueField are present in several hardware
blocks and each block provides access to these stats either through
counters that can be programmed to monitor supported events or
through memory-mapped registers that hold the relevant information.
The hardware blocks that include a performance module are:
* Tile (block containing 2 cores and a shared L2 cache)
* TRIO (PCIe root complex)
* MSS (Memory Sub-system containing the Memory Controller and L3 cache)
* GIC (Interrupt controller)
* SMMU (System Memory Management Unit)
The mlx_pmc driver provides access to all of these performance modules
through a hwmon sysfs interface.

v2 --> v3
Update copyright info.

v1 --> v2
Remove unused headers.
Add comma to arrays where last line is not a termination.
Use kstrtoint in place of sscanf.
UUID manipulation follows drivers/platform/mellanox/mlxbf-bootctl.c

Signed-off-by: Shravan Kumar Ramani <shravankr@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Link: https://lore.kernel.org/r/4e19a1e5bf4197ad27fc57981fd280eaebd23577.1602160468.git.shravankr@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

platform/mellanox: Add bootctl driver for Mellanox BlueField Soc

This commit adds the bootctl platform driver for Mellanox BlueField
Soc, which queries secure state and controls the eMMC boot partition
swapping by sending SMC calls to ATF running at EL3.

Below are the sequences of typical use case.

1. User requests boot partition swapping, which could be on-demand or
during boot-image upgrade via UEFI capsule;

2. This bootctl driver handles the request and sends SMC call
to ATF. ATF programs register BREADCRUMB0 which has value
preserved during warm reset. It also programs eMMC to swap
the boot partition;

3. After software reset (rebooting), ATF BL1 (BootRom) checks
register BREADCRUMB0 and enable watchdog if configured;

4. If booting fails, the watchdog timer will trigger rebooting.
In such case, ATF Boot ROM will switch the boot partition
back to the previous one. This is a robust feature and used
to prevent failure during boot partition upgrade.

Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
Signed-off-by: Liming Sun <lsun@mellanox.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

platform/mellanox: Add TmFifo driver for Mellanox BlueField Soc

This commit adds the TmFifo platform driver for Mellanox BlueField
Soc. TmFifo is a shared FIFO which enables external host machine
to exchange data with the SoC via USB or PCIe. The driver is based
on virtio framework and has console and network access enabled.

Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
Signed-off-by: Liming Sun <lsun@mellanox.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

platform/mellanox: Introduce support for Mellanox register access driver

Introduce new Mellanox platform driver to allow access to Mellanox
programmable device register space trough sysfs interface.
The driver purpose is to provide sysfs interface for user space for the
registers essential for system control and monitoring.
The sets of registers for sysfs access are supposed to be defined per
system type bases and include the registers related to system resets
operation, system reset causes monitoring and some kinds of mux selection.

Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
[dvhart: Kconfig typo fixes spotted by Randy Dunlap]
Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>

platform/x86: Move Mellanox platform hotplug driver to platform/mellanox

In preparation for making the hotplug driver build for different
architectures, move mlxcpld-hotplug.c to platform/mellanox and the
header to include/linux/platform_data as mlxreg.h to reflect the new
interface changes to come.

Replace references to CPLD with REG throughout the files, consistent
with the new name.

Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
[dvhart: update copyright, rewrite commit message]
Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>