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923fe8ab |
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28-Jan-2022 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Add USB device pinmux settings Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for ports 0 and 1 support USB device mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dfc04955 |
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28-Jan-2022 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Divide pinmux group to support 1ch and 2ch I2S Current pinmux group for audio in/out assumes 4ch I2S case but the UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other ain and aout in the same way. Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8e703784 |
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28-Jan-2022 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Add missing audio pinmux settings for PXs2 SoC Add missing audio I/O pinmux settings for PXs2 SoC. This adds ain1 4ch pins, ain3 and aout1. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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111a8fcb |
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29-Jul-2019 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Separate modem group from UART ctsrts group It depends on the board implementation whether to have each pins of CTS/RTS, and others for modem. So it is necessary to divide current uart_ctsrts group into uart_ctsrts and uart_modem groups. Since the number of implemented pins for modem differs depending on SoC, each uart_modem group also has a different number of pins. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-2-git-send-email-hayashi.kunihiko@socionext.com Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8b78de95 |
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14-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: constify uniphier_pinctrl_socdata These are constant data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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34812fe1 |
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05-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: convert to SPDX License Identifier checkpatch.pl suggests to use SPDX license tag. I am happy to follow it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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24d1c217 |
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19-Jul-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: add spi pin-mux settings Add pin-mux settings for spi controller. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ac316725 |
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19-Jun-2018 |
Randy Dunlap <rdunlap@infradead.org> |
headers: separate linux/mod_devicetable.h from linux/platform_device.h At over 4000 #includes, <linux/platform_device.h> is the 9th most #included header file in the Linux kernel. It does not need <linux/mod_devicetable.h>, so drop that header and explicitly add <linux/mod_devicetable.h> to source files that need it. 4146 #include <linux/platform_device.h> After this patch, there are 225 files that use <linux/mod_devicetable.h>, for a reduction of around 3900 times that <linux/mod_devicetable.h> does not have to be read & parsed. 225 #include <linux/mod_devicetable.h> This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/ Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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4fc97ef9 |
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19-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: add UART hardware flow control pin-mux settings UniPhier SoCs have the following pins for hardware flow control of UART: XRTS, XCTS and for modem control of UART: XDTR, XDSR, XDCD, XRI The port number with the flow control is SoC-dependent. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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38eae3fa |
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13-Mar-2018 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings The UniPhier PXs2 SoC audio core use following 25 pins: ain1 : 2ch I2S input : AI1ADCCK, AI1BCK, AI1D0, AI1LRCK ain2 : 8ch I2S input : AI2ADCCK, AI2BCK, AI2D[0-3], AI2LRCK ainiec1 : S/PDIF input : XIRQ17 (for AO1IEC) aout2 : 8ch I2S output: AO2BCK, AO2D0, AO2DACCK, AO2LRCK PORT226, 227, 230 (for AO2D[1-3]) aout3 : 2ch I2S output: AO3BCK, AO3DMIX, AO3DACCK, AO3LRCK aoutiec1: S/PDIF output : PORT132(for AO1IEC) aoutiec2: S/PDIF output : AO2IEC Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9697509e |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add suspend / resume support Save registers lost in the sleep when suspending, and restore them when resuming. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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7f6ee0a5 |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: clean up GPIO port muxing There are a bunch of GPIO muxing data, but most of them are actually unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges" DT properties. Tables that contain a set of GPIO pins are still needed for the named mapping by "gpio-ranges-group-names". This is a much cleaner way for UniPhier SoC family where GPIO numbers are not straight mapped to pin numbers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2afd450d |
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15-Mar-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: make drivers non-modular At first these drivers were written as tristate, but the module usecases are actually not tested. Make all of them boolean. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8ef364b3 |
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15-Mar-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: remove obsoleted compatibles Since commit 3e030b0b4e46 ("pinctrl: uniphier: allow to have pinctrl node under syscon node"), this driver has kept compatibility for the old DT files. Several releases have passed since then, so remove the obsoleted compatibles and clean up the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1e359ab1 |
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06-Jul-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add Ethernet pin-mux settings Add the following Ethernet interfaces: PH1-LD4: MII, RMII PH1-Pro4: MII, RMII, RGMII PH1-sLD8: MII, RMII (Built-in PHY is also supported) ProXstream2: MII, RMII, RGMII PH1-LD6b: RMII, RGMII PH1-LD11: RMII (Built-in PHY is also supported) PH1-LD20: RMII, RGMII Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3e030b0b |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: allow to have pinctrl node under syscon node Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. To allow to migrate to the new DT structure, this commit adds new compatible strings to not disturb the existing DT. After a while, the old binding will be removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a2456a77 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add System Bus pin-mux settings This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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39ec9ace |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: support pin configuration for dedicated pins PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c2ebf475 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: introduce capability flag The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding the new one. Having just one flag would be better than adding a new struct member every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9eaa98a6 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: rename macros for drive strength control The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Some of the configuration registers on it have 3-bit width. The feature will be supported in the next commit, but a problem is that macro names are getting longer and longer in the current naming scheme. Before moving forward, this commit renames macros as follows: UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4 UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5 UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fc78a566 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: allocate struct pinctrl_desc in probe function Currently, every SoC driver defines struct pinctrl_desc statically, i.e. it consumes memory footprint even if it is not probed. In multi-platform, many pinctrl drivers are linked (generally as built-in objects), although only one of them is actually used. So, it is reasonable to allocate memory dynamically where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4109508a |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: set pinctrl_desc name in common probe function Every SoC driver sets the same name for struct pinctrl_desc and platform_driver. The common probe function can set desc->name instead of duplicating strings in each SoC driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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7d36b245 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: set pinctrl_desc owner in common probe function The owner of the struct pinctrl_desc matches that of platform_driver. Set it in the common probe function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4725774f |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: fix register offsets for drive strength control These pin tables were generated by parsing hardware documents with a script, but the script had a bug. Fix the register offsets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a4c6052b |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: rename function and variable names Make function/variable names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1ac471ed |
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24-Feb-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: uniphier: Use devm_pinctrl_register() for pinctrl registration Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1233a1fb |
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01-Mar-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: rename CONFIG options and file names The current "CONFIG_PINCTRL_UNIPHIER_PH1_*" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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