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dfc04955 |
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28-Jan-2022 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Divide pinmux group to support 1ch and 2ch I2S Current pinmux group for audio in/out assumes 4ch I2S case but the UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other ain and aout in the same way. Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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290e2d18 |
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06-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCs Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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111a8fcb |
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29-Jul-2019 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: Separate modem group from UART ctsrts group It depends on the board implementation whether to have each pins of CTS/RTS, and others for modem. So it is necessary to divide current uart_ctsrts group into uart_ctsrts and uart_modem groups. Since the number of implemented pins for modem differs depending on SoC, each uart_modem group also has a different number of pins. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-2-git-send-email-hayashi.kunihiko@socionext.com Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8b78de95 |
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14-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: constify uniphier_pinctrl_socdata These are constant data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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34812fe1 |
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05-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: convert to SPDX License Identifier checkpatch.pl suggests to use SPDX license tag. I am happy to follow it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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24d1c217 |
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19-Jul-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: add spi pin-mux settings Add pin-mux settings for spi controller. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ac316725 |
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19-Jun-2018 |
Randy Dunlap <rdunlap@infradead.org> |
headers: separate linux/mod_devicetable.h from linux/platform_device.h At over 4000 #includes, <linux/platform_device.h> is the 9th most #included header file in the Linux kernel. It does not need <linux/mod_devicetable.h>, so drop that header and explicitly add <linux/mod_devicetable.h> to source files that need it. 4146 #include <linux/platform_device.h> After this patch, there are 225 files that use <linux/mod_devicetable.h>, for a reduction of around 3900 times that <linux/mod_devicetable.h> does not have to be read & parsed. 225 #include <linux/mod_devicetable.h> This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/ Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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fdab33d5 |
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26-Apr-2018 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
pinctrl: uniphier: add LD11 MPEG2-TS I/O pin-mux settings The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4fc97ef9 |
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19-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: add UART hardware flow control pin-mux settings UniPhier SoCs have the following pins for hardware flow control of UART: XRTS, XCTS and for modem control of UART: XDTR, XDSR, XDCD, XRI The port number with the flow control is SoC-dependent. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a5af5c9f |
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14-Mar-2018 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group This patch divides large pin-mux group 'aio' of UniPhier LD11/LD20 to 2 groups as following: aout1 : 8ch I2S output: AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] aoutiec1: S/PDIF output : AO1IEC, AO1ARC Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0cc449f6 |
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23-Oct-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: remove eMMC hardware reset pin-mux This is handled by the mmc-pwrseq-emmc driver, which controls an eMMC hardware reset via a GPIO line. Remove it from the function pin-mux settings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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abcac84f |
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09-Aug-2017 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
pinctrl: uniphier: add Audio out pin-mux settings The UniPhier LD11/20 SoC audio core use following 8 pins: AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9697509e |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add suspend / resume support Save registers lost in the sleep when suspending, and restore them when resuming. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4e767983 |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: omit redundant input enable bit information For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit number matches its pin number. So, this is redundant information. Instead, we just need a flag to know if the iectrl gating exists or not. With this refactoring, 5 bits in pin data will be saved. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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7f6ee0a5 |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: clean up GPIO port muxing There are a bunch of GPIO muxing data, but most of them are actually unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges" DT properties. Tables that contain a set of GPIO pins are still needed for the named mapping by "gpio-ranges-group-names". This is a much cleaner way for UniPhier SoC family where GPIO numbers are not straight mapped to pin numbers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9592bc25 |
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13-Jun-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11 The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2afd450d |
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15-Mar-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: make drivers non-modular At first these drivers were written as tristate, but the module usecases are actually not tested. Make all of them boolean. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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96e1ce8f |
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20-Feb-2017 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
pinctrl: uniphier: change pin names of aio/xirq for LD11 This patch changes pin names of AIO and XIRQ according to updated specification. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1e359ab1 |
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06-Jul-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add Ethernet pin-mux settings Add the following Ethernet interfaces: PH1-LD4: MII, RMII PH1-Pro4: MII, RMII, RGMII PH1-sLD8: MII, RMII (Built-in PHY is also supported) ProXstream2: MII, RMII, RGMII PH1-LD6b: RMII, RGMII PH1-LD11: RMII (Built-in PHY is also supported) PH1-LD20: RMII, RGMII Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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cf9a2f63 |
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29-Jun-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 This SoC has no SD card controller. Nor does it have USB port3. These pin-mux settings have no point. Fixes: 70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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96c8b690 |
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15-Jun-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: prohibit drive control for pin 61-66 of PH1-LD11 According to the hardware document, setting the drive control is prohibited for these pins (N-channel Open Drain pins). Set their drive control attribute to "fixed". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9467f568 |
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06-Jun-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: fix NAND pin-mux settings for PH1-LD11/LD20 My mistake in the initial support patches. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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70f2f9c4 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD11 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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