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8be586f7 |
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27-Sep-2023 |
Linus Walleij <linus.walleij@linaro.org> |
Revert "pinctrl: tegra: Add support to display pin function" This reverts commit d1cd5b51bc9152dc2b63c5f843590272d6694d50. It was reported that some I2C3 functions stop working after this patch, and it is just debug help so let's revert it and investigate. Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d1cd5b51 |
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14-Jul-2023 |
Prathamesh Shete <pshete@nvidia.com> |
pinctrl: tegra: Add support to display pin function The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fad57233 |
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29-May-2023 |
Thierry Reding <treding@nvidia.com> |
pinctrl: tegra: Duplicate pinmux functions table The function table is filled with group information based on other instance-specific data at runtime. However, the function table can be shared between multiple instances, causing the ->probe() function for one instance to overwrite the table of a previously probed instance. Fix this by sharing only the function names and allocating a separate function table for each instance. Fixes: 5a0047360743 ("pinctrl: tegra: Separate Tegra194 instances") Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230530105308.1292852-1-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5a004736 |
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04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
pinctrl: tegra: Separate Tegra194 instances Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8d886bba |
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18-Oct-2021 |
Suresh Mangipudi <smangipudi@nvidia.com> |
pinctrl: tegra: include lpdr pin properties Update lpdr pin-property for supported pins. lpdr property help disable most basic driver fingers leaving only minimal base driver finger. Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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368b62f2 |
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19-Mar-2020 |
Thierry Reding <treding@nvidia.com> |
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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66539e6e |
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19-Mar-2020 |
Thierry Reding <treding@nvidia.com> |
pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo Properly spell "Schmitt" in the kerneldoc for pin group definitions. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9870acd3 |
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31-Jul-2019 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
pinctrl: tegra: Add suspend and resume support This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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cf75b8f2 |
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21-Jun-2019 |
Thierry Reding <treding@nvidia.com> |
pinctrl: tegra: Add bitmask support for parked bits Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2025cf9e |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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b4e18ba2 |
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16-May-2019 |
Krishna Yarlagadda <kyarlagadda@nvidia.com> |
pinctrl: tegra: Support 32 bit register access Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3c94d2d0 |
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26-Jul-2018 |
Stefan Agner <stefan@agner.ch> |
pinctrl: tegra: define GPIO compatible node per SoC Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c5948707 |
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03-May-2018 |
Dmitry Osipenko <digetx@gmail.com> |
pinctrl: tegra20: Provide CDEV1/2 clock muxes Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0bde4897 |
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23-May-2016 |
Linus Walleij <linus.walleij@linaro.org> |
Revert "Revert "pinctrl: tegra: avoid parked_reg and parked_bank"" This reverts commit 0d5358330c20d50e52e3e65ff07a5db8007041fc.
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0d535833 |
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12-May-2016 |
Linus Walleij <linus.walleij@linaro.org> |
Revert "pinctrl: tegra: avoid parked_reg and parked_bank" This reverts commit 1d18a3f0f0809f6c71f1f6e9e268ee904ce0b588.
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1d18a3f0 |
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02-May-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: tegra: avoid parked_reg and parked_bank NVIDIA's Tegra210 support the park bit to make pinmux configuration enable/disable. If parked bit is 1 then configuration does not apply and if it is 0 then pinmux configuration applies. This is to support to avoid any glitch in pinmux configurations. The parked bit is part of mux register and mux bank and hence it is not required to have member for the parked_reg and parked bank very similar to other bit field of the same register. Remove the need of the parked register and parked bank and get whether parked function supported or not by parked_bit. This is to make the parked bit handling same as other fields of mux registers. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f1daa8a1 |
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24-Feb-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: tegra: Use devm_pinctrl_register() for pinctrl registration Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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26e6aaaf |
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07-Apr-2016 |
Rhyland Klein <rklein@nvidia.com> |
pinctrl: tegra: clear park bit for all pins Parking bits might not be cleared by the bootloader properly (if for instance it doesn't use the device configured by that pin). Clear the park bits for all the pins during pinctrl probe. This is present on T210 platforms but not earlier ones, so for earlier generations, set parked_reg = -1 to disable. The park bit is used to prevent glitching when reprogramming pinctrl registers. Based on work by: Shravani Dingari <shravanid@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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25cbac77 |
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23-Jan-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: tegra: move Tegra pinctrl drivers to sub-directory Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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