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060f03e9 |
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14-Jul-2023 |
Rob Herring <robh@kernel.org> |
pinctrl: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fb18f188 |
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27-Jul-2019 |
Icenowy Zheng <icenowy@aosc.io> |
pinctrl: sunxi: v3s: introduce support for V3 Introduce the GPIO pins that is only available on V3 (not on V3s) to the V3s pinctrl driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://lore.kernel.org/r/20190728031227.49140-2-icenowy@aosc.io Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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35817d34 |
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16-Mar-2018 |
Icenowy Zheng <icenowy@aosc.io> |
pinctrl: sunxi: change irq_bank_base to irq_bank_map The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f547b3de |
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01-Aug-2017 |
Icenowy Zheng <icenowy@aosc.io> |
pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base The V3s pin controller doesn't have the bank 0 (starts at address 0x200), which is like A33. However, this is not worked around when developing the driver, which makes IRQ not working. Fix the IRQ bank base. Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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56d9e4a7 |
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03-Jan-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
pinctrl: sunxi: add driver for V3s SoC V3s SoC features only a pin controller (for the lack of CPUs part). Add a driver for this controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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