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a6f06b90 |
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20-Feb-2024 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Allow the compiler to optimize away sh_pfc_pm The conversion to DEFINE_NOIRQ_DEV_PM_OPS() lost the ability of the compiler to optimize away the struct dev_pm_ops object when it is not needed. Fix this by replacing the use of pm_sleep_ptr() by a custom wrapper. Fixes: 727eb02eb753375e ("pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/6238a78e32fa21f0c795406b6cba7bce7af92577.1708513940.git.geert+renesas@glider.be
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#
291f7856 |
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26-Jan-2024 |
Cong Dang <cong.dang.xn@renesas.com> |
pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC support Add initial pin control support for the R-Car V4M (R8A779H0) SoC, including bias, drive strength and voltage control. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> [geert: Fixes and cleanups] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5f59263e75be713dc954007cfeb2c99274c9d761.1706264667.git.geert+renesas@glider.be
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3803584a |
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22-Jan-2024 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Limit cfg reg enum checks to provided IDs If the number of provided enum IDs in a variable width config register description does not match the expected number, the checker uses the expected number for validating the individual enum IDs. However, this may cause out-of-bounds accesses on the array holding the enum IDs, leading to bogus enum_id conflict warnings. Worse, if the bug is an incorrect bit field description (e.g. accidentally using "12" instead of "-12" for a reserved field), thousands of warnings may be printed, overflowing the kernel log buffer. Fix this by limiting the enum ID check to the number of provided enum IDs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c7385f44f2faebb8856bcbb4e908d846fc1531fb.1705930809.git.geert+renesas@glider.be
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#
727eb02e |
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17-Jul-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230717172821.62827-10-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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060f03e9 |
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14-Jul-2023 |
Rob Herring <robh@kernel.org> |
pinctrl: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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45e6cc8e |
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21-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: core: Drop unneeded #ifdef CONFIG_OF As the of_node member of struct device always exists, and there is a dummy of of_device_get_match_data() for the !CONFIG_OF case, there is no longer a need to protect code using these interfaces with an #ifdef. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/55d72ce46b43ec2f41681cb5ba7ca7fcebdb98d1.1679416005.git.geert+renesas@glider.be
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0256b6ae |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Annotate sentinels in tables It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Hence drop all such commas. Add comments to clarify the purpose of the empty elements. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/845f1d8285dd44522af1b0f429d4c6bd4759eb9e.1678272180.git.geert+renesas@glider.be
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#
b88e733a |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Currently, the Renesas pin control driver supports pins that can switch their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. However, some SoCs have pins that can switch between 1.8V and 2.5V. Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE capability and voltage level flags by a 2-bit field, to cover three possible I/O voltage switching options. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert+renesas@glider.be
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#
47ea7ff1 |
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07-Mar-2023 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
pinctrl: renesas: Remove R-Car H3 ES1.* handling R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230307105645.5285-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
ad9bb2fe |
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30-Jun-2022 |
LUU HOAI <hoai.luu.ub@renesas.com> |
pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support This patch adds initial pinctrl support for the R-Car V4H (R8A779G0) SoC, including bias, drive strength and voltage control. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
fc883ed5 |
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13-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Add reserved field checks Add checks for discovering registers with reserved fields that could benefit from being described using variable-width reserved field shorthands, reducing kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
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#
62109055 |
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13-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Add shorthand for reserved register fields Currently, reserved register fields must be fully described using dummy enum IDs (zeroes), one for each possible state (2^bits states). Add support for describing reserved fields using negative field width values as shorthands, thus removing the need for dummy values. Apart from the obvious size reduction due to the removal of the dummy values, this will also enable merging adjacent reserved fields into a single field, reducing the number of fields to describe, and thus kernel size. Update the checker accordingly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cad7c92ef039d9a4d039807efc15886a7aa862be.1649865241.git.geert+renesas@glider.be
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#
5376e3d9 |
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29-Apr-2022 |
Yang Yingliang <yangyingliang@huawei.com> |
pinctrl: renesas: core: Fix possible null-ptr-deref in sh_pfc_map_resources() It will cause null-ptr-deref when using 'res', if platform_get_resource() returns NULL, so move using 'res' after devm_ioremap_resource() that will check it to avoid null-ptr-deref. And use devm_platform_get_and_ioremap_resource() to simplify code. Fixes: c7977ec4a336 ("pinctrl: sh-pfc: Convert to platform_get_*()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220429082637.1308182-1-yangyingliang@huawei.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
dd035683 |
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19-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Rework drive and bias pin iteration The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5051ae56a1388ccf2d283dfc9624de2991cce914.1650355619.git.geert+renesas@glider.be
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#
030ac6d7 |
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21-Feb-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Initial R8A779F0 PFC support Add initial Pin Function Controller (PFC) support for the Renesas R-Car S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/fd8201da404b7b0897130b254380ffc97f437266.1645457792.git.geert+renesas@glider.be
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#
de9b8610 |
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21-Feb-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Fix miscalculation of number of states The checker failed to validate all enum IDs in the description of a register with fixed-width register fields, due to a miscalculation of the number of described states: each register field of n bits can have "1 << n" possible states, not "1". Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked (SH-Mobile AG5 has more than 4000 enum IDs defined). Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6d8a6a05564f38f9d20464c1c17f96e52740cf6a.1645460429.git.geert+renesas@glider.be
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4704797e |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Check drive pin conflicts Check that there is only a single entry for each pin with drive strength capabilities. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/382206e737710afd3059abe75bc41e324823e657.1640270559.git.geert+renesas@glider.be
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6bfbaec7 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Check bias pin conflicts Check that there is only a single entry for each pin with pull-up and/or pull-down capabilities. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dbda76f342258f8029f0420fbe3f341a9abd6f01.1640270559.git.geert+renesas@glider.be
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#
8d1c50b8 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Validate I/O voltage configs consistency Validate consistency of the pin control tables for pins with I/O voltage capabilities. If a pin has I/O voltage register bits declarations through .pin_to_pocctrl(), the SH_PFC_PIN_CFG_IO_VOLTAGE flag should be set in the pin's configs, and vice versa. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/de81cced01ae3f26d341177d66d4b8e918fbfb76.1640270559.git.geert+renesas@glider.be
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#
854476b8 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Validate drive strength configs consistency Validate consistency of the pin control tables for pins with drive strength capabilities. If a pin has drive strength register bits declarations in drive_regs[], the SH_PFC_PIN_CFG_DRIVE_STRENGTH flag should be set in the pin's configs, and vice versa. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0d5de01b5fe2c5fd23c3bea41077dc57ad105b9e.1640270559.git.geert+renesas@glider.be
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#
4eb5a6ee |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Validate bias configs consistency Validate consistency of the pin control tables for pins with pull-up and/or pull-down capabilities. If a pin has bias register bits declarations in bias_regs[] or through .pin_to_portcr(), the corresponding SH_PFC_PIN_CFG_PULL* flags should be set in the pin's configs, and vice versa, and the .get_bias() and .set_bias() callbacks should be implemented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19b3e0773fbb36c015a43db683f79e75b0fec3ee.1640270559.git.geert+renesas@glider.be
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4bb9514c |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Add pin group sharing checks Add checks for discovering pin groups that could share pin data, as sharing reduces kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e16fdf729156e13b591d2f082f2cc934da580074.1640270559.git.geert+renesas@glider.be
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27b32fbb |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Simplify same_name() Simplify the helper that checks if two strings are valid and identical. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/509c70041bcf4302e284758abe1fd8165644b505.1640270559.git.geert+renesas@glider.be
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f4e260bf |
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07-Oct-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Prefix common checker output Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for easier grepping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
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f31a5ffb |
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07-Oct-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Fix bias checks on SoCs with pull-down only pins If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be
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e212923e |
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07-Oct-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Move overlapping field check Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be
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28e7f8ff |
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07-Oct-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Fix off-by-one bug in drive register check The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e07ad0a1ec ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be
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412da8c7 |
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07-Oct-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Fix save/restore on SoCs with pull-down only pins If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be
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075667cc |
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06-Sep-2021 |
Jason Wang <wangborong@cdjrlc.com> |
pinctrl: renesas: No need to initialise global statics Global static variables don't need to be initialized to 0, because the compiler will initialize them. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Link: https://lore.kernel.org/r/20210906134040.96642-1-wangborong@cdjrlc.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
91d1be9f |
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19-Jul-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Fix pin control matching on R-Car H3e-2G As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
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#
b82fd2df |
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03-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() static Now all R-Car pin control drivers have been converted to the common R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a single place. Move it from core.c to pinctrl.c, make it static, and rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
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741a7370 |
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12-Jan-2021 |
Ulrich Hecht <uli+renesas@fpond.eu> |
pinctrl: renesas: Initial R8A779A0 (V3U) PFC support This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC, including bias, drive strength and voltage control. Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
e127ef2e |
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12-Jan-2021 |
Ulrich Hecht <uli+renesas@fpond.eu> |
pinctrl: renesas: Implement unlock register masks The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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6dd169fc |
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11-Jan-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: checker: Restrict checks to Renesas platforms When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin control driver runs sanity checks against the pin control tables. This may cause lots of output on the console, and can be annoying in ARM multi-platform kernels. Fix this by only running the checks when running on SuperH, or on a DT platform supported by the Renesas pin controller driver. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
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7b1425f0 |
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28-Oct-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
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077365a9 |
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09-Sep-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: Rename sh-pfc to renesas The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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