History log of /linux-master/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
Revision Date Author Comments
# 9e863d27 29-Nov-2023 Andy Shevchenko <andriy.shevchenko@linux.intel.com>

pinctrl: qcom: lpass-lpi: Remove unused member in struct lpi_pingroup

The group is not used anywhere, remove it. And if needed, it should be
struct pingroup anyway.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231129161459.1002323-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 2cd57cbd 29-Nov-2023 Andy Shevchenko <andriy.shevchenko@linux.intel.com>

pinctrl: qcom: lpass-lpi: Replace kernel.h with what is being used

Replace kernel.h with what exactly is being used, i.e. array_size.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231129161459.1002323-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 6ea5c72b 13-Oct-2023 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register

Existing Qualcomm SoCs have the LPASS pin controller slew rate control
in separate register, however this will change with upcoming Qualcomm
SoCs. The slew rate will be part of the main register for pin
configuration, thus second device IO address space is not needed.

Prepare for supporting new SoCs by adding flag customizing the driver
behavior for slew rate.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231013145935.220945-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 776d54c1 09-Oct-2023 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

pinctrl: qcom/lpi: Convert to platform remove callback returning void

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.

To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().

To convert all those qcom pinctrl drivers, make msm_pinctrl_remove()
return void (instead of zero) and use .remove_new in all drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20231009162510.335208-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# aa9430f8 07-Oct-2022 Andy Shevchenko <andriy.shevchenko@linux.intel.com>

pinctrl: qcom: Add missing header(s)

Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.

While at it, sort headers alphabetically.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>


# bb2c2fe7 29-Jun-2022 Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

pinctrl: qcom: sc7280: Fix compile bug

Fix the compilation error, caused by updating constant variable.
Hence remove redundant constant variable, which is no more useful
as per new design.

The issue is due to some unstaged changes. Fix it up.

Fixes: 36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# a6a5c173 18-Apr-2022 Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

pinctrl: qcom: Update clock voting as optional

Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, as these macro and dcodec GDSC switches are
maintained as power domains and operated from lpass clock drivers.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 9ce49018 18-Apr-2022 Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

pinctrl: qcom: Extract chip specific LPASS LPI code

Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>