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ff629d30 |
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15-Dec-2023 |
Wang Jinchao <wangjinchao@xfusion.com> |
pinctrl: qcom: lpass-lpi: remove duplicated include remove the second #include <linux/seq_file.h> Signed-off-by: Wang Jinchao <wangjinchao@xfusion.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/202312151810+0800-wangjinchao@xfusion.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6ea5c72b |
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13-Oct-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231013145935.220945-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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28bb7c55 |
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13-Oct-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: split slew rate set to separate function Setting slew rate for each pin will grow with upcoming Qualcomm SoCs, so split the code responsible for this into separate function for easier readability and maintenance. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231013145935.220945-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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776d54c1 |
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09-Oct-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: qcom/lpi: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-2-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c8befdc4 |
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13-Oct-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: fix concurrent register updates The Qualcomm LPASS LPI pin controller driver uses one lock for guarding Read-Modify-Write code for slew rate registers. However the pin configuration and muxing registers have exactly the same RMW code but are not protected. Pin controller framework does not provide locking here, thus it is possible to trigger simultaneous change of pin configuration registers resulting in non-atomic changes. Protect from concurrent access by re-using the same lock used to cover the slew rate register. Using the same lock instead of adding second one will make more sense, once we add support for newer Qualcomm SoC, where slew rate is configured in the same register as pin configuration/muxing. Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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060f03e9 |
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14-Jul-2023 |
Rob Herring <robh@kernel.org> |
pinctrl: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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abf02e13 |
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14-Jul-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
pinctrl: qcom: lpass-lpi: Make the clocks optional, always Some platforms provide a single clock source to all LPASS peripherals, others provide two, and there are probably others that provide it through magic invisible-to-Linux wires. Rely on bindings to mandate the adequate number of clocks necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fae1466d |
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09-Mar-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: allow glitch-free output GPIO When choosing GPIO function for pins, use the same glitch-free method as main TLMM pinctrl-msm.c driver in msm_pinmux_set_mux(). This replicates the commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output") to LPASS pin controller with same justification. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230309154949.658380-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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926cf596 |
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09-Mar-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: use consistent name for "group" variable The set_mux callback in SoC TLMM driver (pinctrl-msm.c) uses "group", not "group_num" for the number of the pin group. Other places of lpass-lpi also use "group", so let's be consistent for code readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230309154949.658380-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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163bfb0c |
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09-Mar-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
pinctrl: qcom: lpass-lpi: set output value before enabling output As per Hardware Programming Guide, when configuring pin as output, set the pin value before setting output-enable (OE). Similar approach is in main SoC TLMM pin controller. Cc: <stable@vger.kernel.org> Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230309154949.658380-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a3fc976a |
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12-Jan-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: qcom: lpass-lpi: Remove duplicate assignment of of_gpio_n_cells The of_gpio_n_cells default is 2 when ->of_xlate() callback is not defined. No need to assign it explicitly in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230112184923.80442-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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03e9491f |
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27-Oct-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: qcom: lpass-lpi: Add missed bitfield.h Previously the cleanup change dropped the bitfield.h from the pinctrl-lpass-lpi.h, since it's not used there, but forgot to re-instantiate it in the C-file, where users are located. Fix this by adding missed bitfield.h to the C-file. Fixes: aa9430f8a6de ("pinctrl: qcom: Add missing header(s)") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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aa9430f8 |
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07-Oct-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: qcom: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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bb2c2fe7 |
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29-Jun-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: sc7280: Fix compile bug Fix the compilation error, caused by updating constant variable. Hence remove redundant constant variable, which is no more useful as per new design. The issue is due to some unstaged changes. Fix it up. Fixes: 36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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61a2cc09 |
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27-Jun-2022 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: qcom: sc7280: Fix compile bug The idea was right but the code was breaking in next. I assume some unstaged commit was involed. Fix it up. Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Cc: Stephen Boyd <swboyd@chromium.org> Fixes: 36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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36fe2684 |
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10-Jun-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets Update lpass lpi pin control driver, with clock optional check for ADSP disabled platforms. This check required for distingushing ADSP based platforms and ADSP bypass platforms. In case of ADSP enabled platforms, where audio is routed through ADSP macro and decodec GDSC Switches are triggered as clocks by pinctrl driver and ADSP firmware controls them. So It's mandatory to enable them in ADSP based solutions. In case of ADSP bypass platforms clock voting is optional as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1654921357-16400-3-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a6a5c173 |
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18-Apr-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: Update clock voting as optional Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9ce49018 |
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18-Apr-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: Extract chip specific LPASS LPI code Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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be73368d |
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18-Apr-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: Update lpi pin group custiom functions with framework generic functions Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-5-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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64547110 |
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18-Apr-2022 |
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> |
pinctrl: qcom: Update macro name to LPI specific Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2a9be380 |
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04-Mar-2021 |
Jonathan Marek <jonathan@marek.ca> |
pinctrl: qcom: lpass lpi: use default pullup/strength values If these fields are not set in dts, the driver will use these variables uninitialized to set the fields. Not only will it set garbage values for these fields, but it can overflow into other fields and break those. In the current sm8250 dts, the dmic01 entries do not have a pullup setting, and might not work without this change. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210304194816.3843-1-jonathan@marek.ca Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6e261d10 |
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02-Dec-2020 |
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> |
pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org [Add some dependencies] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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