pinctrl: Add driver support for Amlogic T7 SoCs

Add a new pinctrl driver for Amlogic T7 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20230922094342.637251-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: Add driver support for Amlogic C3 SoCs

Add a new pinctrl driver for Amlogic C3 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson: add pinctrl driver support for Meson-S4 Soc

Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson: add pinctrl driver support for Meson-A1 SoC

Meson A1 SoC share the same register layout of pinmux with previous
Meson-G12A, however there is difference for gpio and pin config register
in A1. The main difference is that registers before A1 are grouped by
function while those of A1 are by bank. The new register layout is as
below:

/* first bank */ /* addr */
- P_PADCTRL_GPIOP_I base + 0x00 << 2
- P_PADCTRL_GPIOP_O base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2
- P_PADCTRL_GPIOP_DS base + 0x05 << 2

/* second bank */
- P_PADCTRL_GPIOB_I base + 0x10 << 2
- P_PADCTRL_GPIOB_O base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2
- P_PADCTRL_GPIOB_DS base + 0x15 << 2

Each bank contains at least 6 registers to be configured, if one bank
has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
,0x25 according to above register layout. For previous chips, registers
are grouped according to their functions while registers of A1 are
according to bank.Also note that there is no AO bank any more in A1.

Current Meson pinctrl driver can cover such change by using base address
of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Socs that do not support drive-strength
like AXG.To make things simple, add an extra dt parser function for
a1 and remain the old dt parser function for only reg parsing.

Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

pinctrl: meson-g12a: add pinctrl driver support

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC

Add new pinctrl driver for Amlogic's Meson-AXG SoC.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC

The pin controller has been updated in the Amlogic Meson AXG series,
which use continuous 4-bit register to select function for each pin.
In order to support this, a new pinmux operations "meson_axg_pmx_ops"
has been added.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson: rework pinmux ops

This change prepare the introduction of new meson SoC. This new SoC will
share the same gpio/pinconf registers but the pinmux part will be
different. While the format of the data associated with each pinmux group
will change, the way to handle pinmuxing will be similar.

To deal with this new situation, the meson_pmx_struture is kept but the
data associated to it is now generic. This allows to reuse the basic
functions which would otherwise be copy/pasted in each pinmux driver
(such as getting the name a count of groups and functions) Only the
functions actually using this specific data is taken out of the common
code and is handling the SoC pinmuxing

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson: separate soc drivers

When meson pinctrl is enabled, all meson platforms pinctrl drivers are
built in the kernel, with a significant amount of data.

This leads to situation where pinctrl drivers targeting an architecture
are also compiled and shipped on another one (ex: meson8 - ARM - compiled
and shipped on ARM64 builds). This is a waste of memory we can easily
avoid.

This change makes 4 pinctrl drivers (1 per SoC) out the original single
driver, allowing to compile and ship only the ones required.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: meson: Add GXL pinctrl definitions

Add support for the Amlogic Meson GXL SoC, this is a partially complete
definition only based on the Amlogic Vendor tree.

This definition differs a lot from the GXBB and needs a separate entry.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC

This patch adds the basic platform file to support the pin controller
found on the Amlogic Meson GXBB SoCs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: Add support for Meson8b

This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: add driver for Amlogic Meson SoCs

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>