#
e1ff91f9 |
|
11-Nov-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
pinctrl: mediatek: Fix EINT pins input debounce time configuration The External Interrupt Controller (EINTC) on all of the supported MediaTek SoCs does support input debouncing, but not all of them index the debounce time values (DBNC_SETTING registers) the same way. Before this change, in some cases, as an example, requesting a debounce time of 16 milliseconds would mistakenly set the relative DBNC_SETTING register to 0x2, resulting in a way shorter debounce time of 500uS. To fix the aforementioned issue, define three different debounce_time arrays, reflecting the correct register index for each value and for each register index variant, and make sure that each SoC pinctrl driver uses the right one. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
57972641 |
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16-Oct-2020 |
Frank Wunderlich <frank-w@public-files.de> |
pinctrl: mt7622: drop pwm ch7 as mt7622 only has 6 channels mt7622 is reported by mediatek to have only 6 pwm channels so drop pindefines for 7th channel Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20201016204019.2606-4-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
19f599e8 |
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22-Sep-2020 |
Chuanhong Guo <gch981213@gmail.com> |
pinctrl: mediatek: mt7622: add antsel pins/groups These pins are named ANTSEL[0~29] in datasheet and are used by wmac for various functions. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200922164159.120920-1-gch981213@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b7d7f9ee |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: extend struct mtk_pin_desc which per-pin driver depends on Because the pincrl-mtk-common.c is an implementation for per-pin binding, its pin descriptor includes more information than pinctrl-mtk-common-v2 so far can support. So, we complement these data before writing a driver using pincrl-mtk-common-v2.c for per-pin binding. By the way, the size of struct mtk_pin_desc would be larger than struct pinctrl_pin_desc can hold, so it's necessary to have a copy before the pins information is being registered into the core. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2bc47dfe |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c Certain SoC own multiple register base for accessing each pin groups, it's easy to be done with extend struct mtk_pin_field_calc to support the kind of SoC such as MT8183. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
182c842f |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add ies register support to pinctrl-mtk-common-v2.c Certain SoCs have to program an extra IES register to configure input enabled mode so that we add it in the existing path as an option. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
85430152 |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add pull related support to pinctrl-mtk-common-v2.c Put pull control support related functions to pinctrl-mtk-common-v2.c as these operations might be different by chips and allow different type of driver to reuse them. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c2832197 |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add driving strength related support to pinctrl-mtk-common-v2.c Put driving strength support related functions to pinctrl-mtk-common-v2.c as these operations might be different by chips and allow different type of driver to reuse them. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1dc5e536 |
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08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: extend struct mtk_pin_soc to pinctrl-mtk-common-v2.c Add two parameters gpio_m and eint_m for configuring GPIO mode and EINT mode, they might be varying depend on SoC. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fb5fa8dc |
|
08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c This patch introduces a data structure mtk_pin_desc, which is used to provide information per pin characteristic such as driving current, eint number and a driving index, that is used to lookup table describing the details about the groups of driving current by which the pin is able to adjust the driving strength so that the driver could get the appropriate driving group when calls .pin_config_get()/set(). Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b906faf7 |
|
08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: extend struct mtk_pin_field_calc to pinctrl-mtk-common-v2.c This patch adds members sz_reg fixed in struct mtk_pin_field_calc - The 'fixed' is used to represent the consecutive pins share the same bits within the same register with the 1st pin so that it can largely reduce the entry size a bit. - The 'sz_reg' is used to indicate the range of bits we use in a register that may vary by SoC The above changes make the code more generic and this is useful as there might be other existing or future chips all use the same logic to access their register set and then being a little more abstract could help in the long run. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e78d57b2 |
|
08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings Add a generic driver pinctrl-moore.c for MT762x SoC and any other SoC that would like to use generic dt-binding. The patch is furtherly refactored from pinctrl-mt7622.c that totally uses the functions back by the generic pinctrl core such as GENERIC_PINCONF, GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS and its binding also completely follows up pinctrl-bindings.txt in Documentation/devicetree/bindings/pinctrl/ to implement. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a1a503a8 |
|
08-Sep-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add pinctrl-mtk-common-v2 for all MediaTek pinctrls Irregular register arrangement and distinct logic access from various MediaTek SoCs would cause pinctrl-mtk-common to bloat and really hard to maintain in the future so that the patch creates pinctrl-mtk-common-v2 based on the core of mt7622-pinctrl. The goals pinctrl-mtk-common-v2 want to achieve are to hopefully support all of MediaTek SoCs, and two kinds of dt-bindings being supported, Linux generic pinctrl dt-binding mt7622 supports and MediaTek per-pin dt-binding the other SoCs support the MT8183 and MT6765 incline to make use of. The patch starts to refactor MT7622 pinctrl driver first with splitting out these portable ways from there such as table-based register operation and drive strength control that is common in both kinds of driver. Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1c5fb66a |
|
13-Sep-2018 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: Include <linux/gpio/driver.h> nothing else These drivers are GPIO drivers, and the do not need to use the legacy header in <linux/gpio.h>, go directly for <linux/gpio/driver.h> instead. Replace any use of GPIOF_* with 0/1, these flags are for consumers, not drivers. Get rid of a few gpio_to_irq() users that was littering around the place, use local callbacks or avoid using it at all. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
238262af |
|
11-Jul-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: Fix probe fail by misuse the selector After the commit acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") and the commit 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver"), it's necessary to add the fixes needed for the pin controller drivers to use the appropriate returned selector for a negative error number returned in case of the fail at these functions. Otherwise, the driver would have a failed probe and that causes boot message cannot correctly output and devices fail to acquire their own pins. Cc: Kevin Hilman <khilman@baylibre.com> Fixes: acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") Fixes: 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e12fa73c |
|
05-Jul-2018 |
Gustavo A. R. Silva <gustavo@embeddedor.com> |
pinctrl: mt7622: mark expected switch fall-through In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 2 was used: -Wimplicit-fallthrough=2 Addresses-Coverity-ID: 1463284 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5b1c4bf2 |
|
21-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: fix a kernel panic when gpio-hog is being applied When we are explicitly using GPIO hogging mechanism in the pinctrl node, such as: &pio { line_input { gpio-hog; gpios = <95 0>, <96 0>, <97 0>; input; }; }; A kernel panic happens at dereferencing a NULL pointer: In this case, the drvdata is still not setup properly yet when it is being accessed. A better solution for fixing up this issue should be we should obtain the private data from struct gpio_chip using a specific gpiochip_get_data instead of a generic dev_get_drvdata. [ 0.249424] Unable to handle kernel NULL pointer dereference at virtual address 000000c8 [ 0.257818] Mem abort info: [ 0.260704] ESR = 0x96000005 [ 0.263869] Exception class = DABT (current EL), IL = 32 bits [ 0.270011] SET = 0, FnV = 0 [ 0.273167] EA = 0, S1PTW = 0 [ 0.276421] Data abort info: [ 0.279398] ISV = 0, ISS = 0x00000005 [ 0.283372] CM = 0, WnR = 0 [ 0.286440] [00000000000000c8] user address but active_mm is swapper [ 0.293027] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 0.298795] Modules linked in: [ 0.301958] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.16.0-rc1+ #389 [ 0.308716] Hardware name: MediaTek MT7622 RFB1 board (DT) [ 0.314396] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 0.319362] pc : mtk_hw_pin_field_get+0x28/0x118 [ 0.324140] lr : mtk_hw_set_value+0x30/0x104 [ 0.328557] sp : ffffff800801b6d0 [ 0.331983] x29: ffffff800801b6d0 x28: ffffff80086b7970 [ 0.337484] x27: 0000000000000000 x26: ffffff80087b8000 [ 0.342986] x25: 0000000000000000 x24: ffffffc00324c230 [ 0.348487] x23: 0000000000000003 x22: 0000000000000000 [ 0.353988] x21: ffffff80087b8000 x20: 0000000000000000 [ 0.359489] x19: 0000000000000054 x18: 00000000fffff7c0 [ 0.364990] x17: 0000000000006300 x16: 000000000000003f [ 0.370492] x15: 000000000000000e x14: ffffffffffffffff [ 0.375993] x13: 0000000000000000 x12: 0000000000000020 [ 0.381494] x11: 0000000000000006 x10: 0101010101010101 [ 0.386995] x9 : fffffffffffffffa x8 : 0000000000000007 [ 0.392496] x7 : ffffff80085d63f8 x6 : 0000000000000003 [ 0.397997] x5 : 0000000000000054 x4 : ffffffc0031eb800 [ 0.403499] x3 : ffffff800801b728 x2 : 0000000000000003 [ 0.409000] x1 : 0000000000000054 x0 : 0000000000000000 [ 0.414502] Process swapper/0 (pid: 1, stack limit = 0x000000002a913c1c) [ 0.421441] Call trace: [ 0.423968] mtk_hw_pin_field_get+0x28/0x118 [ 0.428387] mtk_hw_set_value+0x30/0x104 [ 0.432445] mtk_gpio_set+0x20/0x28 [ 0.436052] mtk_gpio_direction_output+0x18/0x30 [ 0.440833] gpiod_direction_output_raw_commit+0x7c/0xa0 [ 0.446333] gpiod_direction_output+0x104/0x114 [ 0.451022] gpiod_configure_flags+0xbc/0xfc [ 0.455441] gpiod_hog+0x8c/0x140 [ 0.458869] of_gpiochip_add+0x27c/0x2d4 [ 0.462928] gpiochip_add_data_with_key+0x338/0x5f0 [ 0.467976] mtk_pinctrl_probe+0x388/0x400 [ 0.472217] platform_drv_probe+0x58/0xa4 [ 0.476365] driver_probe_device+0x204/0x44c [ 0.480783] __device_attach_driver+0xac/0x108 [ 0.485384] bus_for_each_drv+0x7c/0xac [ 0.489352] __device_attach+0xa0/0x144 [ 0.493320] device_initial_probe+0x10/0x18 [ 0.497647] bus_probe_device+0x2c/0x8c [ 0.501616] device_add+0x2f8/0x540 [ 0.505226] of_device_add+0x3c/0x44 [ 0.508925] of_platform_device_create_pdata+0x80/0xb8 [ 0.514245] of_platform_bus_create+0x290/0x3e8 [ 0.518933] of_platform_populate+0x78/0x100 [ 0.523352] of_platform_default_populate+0x24/0x2c [ 0.528403] of_platform_default_populate_init+0x94/0xa4 [ 0.533903] do_one_initcall+0x98/0x130 [ 0.537874] kernel_init_freeable+0x13c/0x1d4 [ 0.542385] kernel_init+0x10/0xf8 [ 0.545903] ret_from_fork+0x10/0x18 [ 0.549603] Code: 900020a1 f9400800 911dcc21 1400001f (f9406401) [ 0.555916] ---[ end trace de8c34787fdad3b3 ]--- [ 0.560722] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 0.560722] [ 0.570188] SMP: stopping secondary CPUs [ 0.574253] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 0.574253] Cc: stable@vger.kernel.org Fixes: d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
de227ed7 |
|
21-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: stop using the deprecated pinctrl_add_gpio_range If the pinctrl node has the gpio-ranges property, the range will be added by the gpio core and doesn't need to be added by the pinctrl driver. But for keeping backward compatibility, an explicit pinctrl_add_gpio_range is still needed to be called when there is a missing gpio-ranges in pinctrl node in old dts files. Cc: stable@vger.kernel.org Fixes: d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ae6efcae |
|
21-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: fix that pinctrl_claim_hogs cannot work To allow claiming hogs by pinctrl, we cannot enable pinctrl until all groups and functions are being added done. Also, it's necessary that the corresponding gpiochip is being added when the pinctrl device is enabled. Cc: stable@vger.kernel.org Fixes: d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8875059d |
|
21-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: fix initialization sequence between eint and gpiochip Because gpichip applied in the driver must depend on mtk eint to implement the input data debouncing and the translation between gpio and irq, it's better to keep logic consistent with mtk eint being built prior to gpiochip being added. Cc: stable@vger.kernel.org Fixes: e6dabd38d8e7 ("pinctrl: mediatek: add EINT support to MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fafa35cc |
|
21-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: fix error path on failing at groups building It should be to return an error code when failing at groups building. Cc: stable@vger.kernel.org Fixes: d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5f591543 |
|
14-Jun-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mt7622: fix a kernel panic when pio don't work as EINT controller The function, external interrupt controller, is made as an optional to mt7622 pinctrl. But if we don't want pio behaves as an external interrupt controller, it would lead to hw->eint not be created properly and then will cause 'kernel NULL pointer' issue when gpiochip try to call .to_irq or .set_config. To fix it, check hw->eint before accessing the member. [ 1.339494] Unable to handle kernel NULL pointer dereference at virtual address 00000010 [ 1.347857] Mem abort info: [ 1.350742] ESR = 0x96000005 [ 1.353905] Exception class = DABT (current EL), IL = 32 bits [ 1.360024] SET = 0, FnV = 0 [ 1.363185] EA = 0, S1PTW = 0 [ 1.366431] Data abort info: [ 1.369405] ISV = 0, ISS = 0x00000005 [ 1.373363] CM = 0, WnR = 0 [ 1.376437] [0000000000000010] user address but active_mm is swapper [ 1.383005] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 1.388748] Modules linked in: [ 1.391897] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.16.0-rc1+ #344 [ 1.398625] Hardware name: MediaTek MT7622 RFB1 board (DT) [ 1.404279] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 1.409221] pc : mtk_eint_find_irq+0x8/0x24 [ 1.413532] lr : mtk_gpio_to_irq+0x20/0x28 [ 1.417749] sp : ffffff800801baf0 [ 1.421161] x29: ffffff800801baf0 x28: ffffff8008792f40 [ 1.426637] x27: ffffff800886b000 x26: ffffff8008615620 [ 1.432113] x25: ffffffc00e4dbdc8 x24: ffffff80087b8000 [ 1.437589] x23: ffffffc00325a000 x22: ffffffc00325a010 [ 1.443066] x21: ffffffc0033dec18 x20: 00000000ffffffea [ 1.448542] x19: ffffffc00e4db800 x18: 0000000000000130 [ 1.454018] x17: 000000000000000e x16: 0000000000000007 [ 1.459494] x15: ffffff80085ee000 x14: 0000000000000001 [ 1.464970] x13: 0000000000000001 x12: 0000000000000010 [ 1.470446] x11: 0101010101010101 x10: 0000000000000880 [ 1.475922] x9 : ffffff800801b990 x8 : ffffffc0030688e0 [ 1.481399] x7 : ffffff80080c0660 x6 : ffffffc00e4dbbb0 [ 1.486875] x5 : 0000000000000000 x4 : 0000000000000000 [ 1.492351] x3 : ffffff80082a92f4 x2 : 00000000fffffffa [ 1.497826] x1 : 0000000000000051 x0 : 0000000000000000 [ 1.503305] Process swapper/0 (pid: 1, stack limit = 0x0000000054e053bd) [ 1.510210] Call trace: [ 1.512727] mtk_eint_find_irq+0x8/0x24 [ 1.516677] mtk_gpio_to_irq+0x20/0x28 [ 1.520539] gpiod_to_irq+0x48/0x60 [ 1.524135] mmc_gpiod_request_cd_irq+0x3c/0xc4 [ 1.528804] mmc_start_host+0x6c/0x8c [ 1.532575] mmc_add_host+0x58/0x7c [ 1.536168] msdc_drv_probe+0x4fc/0x67c [ 1.540121] platform_drv_probe+0x58/0xa4 [ 1.544251] driver_probe_device+0x204/0x44c [ 1.548649] __driver_attach+0x84/0xf8 [ 1.552512] bus_for_each_dev+0x68/0xa0 [ 1.556461] driver_attach+0x20/0x28 [ 1.560142] bus_add_driver+0xec/0x240 [ 1.564002] driver_register+0x98/0xe4 [ 1.567863] __platform_driver_register+0x48/0x50 [ 1.572711] mt_msdc_driver_init+0x18/0x20 [ 1.576932] do_one_initcall+0x98/0x130 [ 1.580886] kernel_init_freeable+0x13c/0x1d4 [ 1.585375] kernel_init+0x10/0xf8 [ 1.588879] ret_from_fork+0x10/0x18 [ 1.592564] Code: a8c67bfd d65f03c0 a9bf7bfd 910003fd (f9400800) [ 1.598849] ---[ end trace 4bbcb7bc30e98492 ]--- [ 1.603677] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 1.603677] cc: Kevin Hilman <khilman@baylibre.com> Cc: stable@vger.kernel.org Fixes: e6dabd38d8e7 ("pinctrl: mediatek: add EINT support to MT7622 SoC") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e6dabd38 |
|
20-May-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add EINT support to MT7622 SoC Add EINT support to MT7622 SoC and the support is made as just an option to MT7622 pinctrl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8b3d9cd4 |
|
09-Jan-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call Make consistent error handling of all mtk_hw_get_value occurrences using propagating error code from the internal instead of creating a new one. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
181cdac0 |
|
09-Jan-2018 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: mt7622: fix potential uninitialized value being returned commit d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") leads to the following static checker warning: drivers/pinctrl/mediatek/pinctrl-mt7622.c:1419 mtk_gpio_get() error: uninitialized symbol 'value'. 1412 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) 1413 { 1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); 1415 int value; 1416 1417 mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); ^^^^^^^^^^^^^^^^ 1418 1419 return !!value; 1420 } The appropriate error handling must be added to avoid the potential error caused by uninitialized value being returned. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d6ed9355 |
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11-Dec-2017 |
Sean Wang <sean.wang@mediatek.com> |
pinctrl: mediatek: add pinctrl driver for MT7622 SoC Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. However, the IO core for the MT7622 SoC is completely distinct from anyone of previous MediaTek SoCs which already had support, such as the hardware internal, register address map and register detailed definition for each pin. Therefore, instead, the driver is being newly implemented by reusing generic methods provided from the core layer with GENERIC_PINCONF, GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code simplicity and rid of superfluous code. Where the function of pins determined by groups is utilized in this driver which can help developers less confused with what combinations of pins effective on the SoC and even reducing the mistakes during the integration of those relevant boards. As the gpio_chip handling is also only a few lines, the driver also implements the gpio functionality directly through GPIOLIB. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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