History log of /linux-master/drivers/pinctrl/berlin/berlin.h
Revision Date Author Comments
# c6114f21 16-May-2018 Jisheng Zhang <Jisheng.Zhang@synaptics.com>

pinctrl: berlin: switch to SPDX license identifier

Use the appropriate SPDX license identifier in the berlin pinctrl
driver source file and drop the previous license text.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 1d48fb6e 13-Oct-2015 Antoine Tenart <atenart@kernel.org>

pinctrl: berlin: fix my family name spelling

My family name contained an accent when I submitted the
Berlin pinctrl series in the first place. There was an
encoding issue when the series was applied. Fix this.

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
[Je me rendis tous les accents aigus]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# d5c79fcb 16-Oct-2015 Jisheng Zhang <jszhang@marvell.com>

pinctrl: berlin: introduce berlin_pinctrl_probe_regmap()

This is to prepare for the next berlin4ct support, where we won't use
simple-mfd any more.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


# 3de68d33 19-May-2014 Antoine Tenart <atenart@kernel.org>

pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs

The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.

Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:

Group Modes Offset Base Offset LSB Bit Width
GSM12 3 sm_base 0x40 0x10 0x2

Ball Group Mode 0 Mode 1 Mode 2
BK4 GSM12 UART0_RX IrDA0_RX GPIO9
BH6 GSM12 UART0_TX IrDA0_TX GPIO10

So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.

As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>