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c40845e3 |
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26-Mar-2024 |
Arnd Bergmann <arnd@arndb.de> |
kbuild: make -Woverride-init warnings more consistent The -Woverride-init warn about code that may be intentional or not, but the inintentional ones tend to be real bugs, so there is a bit of disagreement on whether this warning option should be enabled by default and we have multiple settings in scripts/Makefile.extrawarn as well as individual subsystems. Older versions of clang only supported -Wno-initializer-overrides with the same meaning as gcc's -Woverride-init, though all supported versions now work with both. Because of this difference, an earlier cleanup of mine accidentally turned the clang warning off for W=1 builds and only left it on for W=2, while it's still enabled for gcc with W=1. There is also one driver that only turns the warning off for newer versions of gcc but not other compilers, and some but not all the Makefiles still use a cc-disable-warning conditional that is no longer needed with supported compilers here. Address all of the above by removing the special cases for clang and always turning the warning off unconditionally where it got in the way, using the syntax that is supported by both compilers. Fixes: 2cd3271b7a31 ("kbuild: avoid duplicate warning options") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
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2eda1cde |
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10-Jul-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed: Add AST2600 pinmux support The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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efa56239 |
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27-Jun-2019 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ec8f24b7 |
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19-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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7f07675c |
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10-Dec-2018 |
Nathan Chancellor <nathan@kernel.org> |
pinctrl: aspeed: Wrap -Woverride-init with cc-option Clang does not support this option: warning: unknown warning option '-Woverride-init'; did you mean '-Woverride-module'? [-Wunknown-warning-option] 1 warning generated. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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56e57cb6 |
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30-Aug-2016 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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524594d4 |
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30-Aug-2016 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: Add pinctrl-aspeed-g4 driver A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4d3d0e42 |
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30-Aug-2016 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: Add core support for Aspeed SoCs The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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