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d295ad7e |
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04-Mar-2024 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: aw9523: Make the driver tristate The AW9523 driver fails to build in some allmod configs since the I2C core can be a module, but AW9523 can not. Fix it up by allowing AW9523 to be a module (tristate). Fixes: 576623d70661 ("pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander") Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202403050916.KBtE6eEj-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240305-fix-aw9523-v2-1-2dc50bab2b17@linaro.org
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#
576623d7 |
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01-Mar-2024 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander The Awinic AW9523(B) is a multi-function I2C gpio expander in a TQFN-24L package, featuring PWM (max 37mA per pin, or total max power 3.2Watts) for LED driving capability. It has two ports with 8 pins per port (for a total of 16 pins), configurable as either PWM with 1/256 stepping or GPIO input/output, 1.8V logic input; each GPIO can be configured as input or output independently from each other. This IC also has an internal interrupt controller, which is capable of generating an interrupt for each GPIO, depending on the configuration, and will raise an interrupt on the INTN pin to advertise this to an external interrupt controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: David Bauer <mail@david-bauer.net> Link: https://lore.kernel.org/r/20210624214458.68716-2-mail@david-bauer.net Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240301-awinic-aw9523-v8-1-7ec572f5dfb4@linaro.org
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#
901b277e |
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08-Nov-2023 |
Esteban Blanc <eblanc@baylibre.com> |
pinctrl: tps6594: Add driver for TPS6594 pinctrl and GPIOs TI TPS6594 PMIC has 11 GPIOs which can be used for different functions. This patch adds a pinctrl and GPIO drivers in order to use those functions. Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231108104124.2818275-1-eblanc@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
37c646dc |
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28-Nov-2023 |
Herve Codina <herve.codina@bootlin.com> |
pinctrl: Add support for the Lantic PEF2256 pinmux The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. This kind of component can be found in old telecommunication system. It was used to digital transmission of many simultaneous telephone calls by time-division multiplexing. Also using HDLC protocol, WAN networks can be reached through the framer. This pinmux support handles the pin muxing part (pins RP(A..D) and pins XP(A..D)) of the PEF2256. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231128132534.258459-5-herve.codina@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e99ce780 |
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19-Sep-2023 |
Tzuyi Chang <tychang@realtek.com> |
pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCs The RTD SoCs share a similar design for pinmux and pinconfig. This common pinctrl driver supports different variants within the RTD SoCs. Signed-off-by: Tzuyi Chang <tychang@realtek.com> Link: https://lore.kernel.org/r/20230919101117.4097-2-tychang@realtek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e693b6a8 |
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14-Aug-2023 |
Neil Armstrong <neil.armstrong@linaro.org> |
pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
40ed50cc |
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19-Jun-2023 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: mlxbf3: remove broken Kconfig 'select' The new pinctrl driver selects GPIO_MLXBF3, but that can not be enabled yet because the MELLANOX_PLATFORM symbol does not exist in the tree: WARNING: unmet direct dependencies detected for GPIO_MLXBF3 Depends on [n]: GPIOLIB [=y] && PCI [=n] && (MELLANOX_PLATFORM [=n] && ARM64 [=y] || COMPILE_TEST [=y]) Selected by [y]: - PINCTRL_MLXBF3 [=y] && PINCTRL [=y] && (MELLANOX_PLATFORM [=n] && ARM64 [=y] || COMPILE_TEST [=y]) As it turns out, the pinctlr driver still builds fine without this, so just remove the select statement. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230619082104.699331-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c20e8c5b |
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04-May-2023 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mfd: rk808: Split into core and i2c Split rk808 into a core and an i2c part in preparation for SPI support. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> # for RTC Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230504173618.142075-6-sebastian.reichel@collabora.com Signed-off-by: Lee Jones <lee@kernel.org>
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#
7edfe0ee |
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03-Apr-2023 |
Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> |
pinctrl: Remove Intel Thunder Bay pinctrl driver Remove Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Link: https://lore.kernel.org/r/20230403120235.939-1-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d11f9328 |
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15-Mar-2023 |
Asmaa Mnebhi <asmaa@nvidia.com> |
pinctrl: mlxbf3: Add pinctrl driver support NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs or take the default hardware functionality. Add a driver for the pin muxing. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dc6ae205 |
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17-Mar-2023 |
Arınç ÜNAL <arinc.unal@arinc9.com> |
pinctrl: ralink: move to mediatek as mtmips This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek introduced new SoCs which utilise this platform. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Link: https://lore.kernel.org/r/20230317213011.13656-5-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fd84aaa8 |
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19-Feb-2023 |
Chester Lin <clin@suse.com> |
pinctrl: add NXP S32 SoC family support Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based on NXP's downstream implementation on nxp-auto-linux repo[1]. [1] https://github.com/nxp-auto-linux/linux/tree/bsp35.0-5.15.73-rt/drivers/pinctrl/freescale Signed-off-by: Matthew Nunez <matthew.nunez@nxp.com> Signed-off-by: Phu Luu An <phu.luuan@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@nxp.com> Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20230220023320.3499-3-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
083b0230 |
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13-Jan-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: digicolor: Use proper headers and drop OF dependency The driver doesn't depend on the OF to be complied. Hence the proper header to use is mod_devicetable.h. Replace of*.h with the above mentioned and drop redundant dependency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/20230113143640.24302-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c0f358fd |
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21-Nov-2022 |
Ren Zhijie <renzhijie2@huawei.com> |
pinctrl: pinctrl-loongson2: fix Kconfig dependency If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set, gcc complained about undefined reference: drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all': pinctrl-loongson2.c:(.text+0x1c4): undefined reference to `pinconf_generic_dt_node_to_map' To fix this error, add depends on OF to config PINCTRL_LOONGSON2. Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f73f88ac |
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13-Nov-2022 |
zhanghongchen <zhanghongchen@loongson.cn> |
pinctrl: pinctrl-loongson2: add pinctrl driver support The Loongson-2 SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing. There is currently no support for GPIO pin pull-up and pull-down. Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn> Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ba7fdf88 |
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30-Sep-2022 |
Jianlong Huang <jianlong.huang@starfivetech.com> |
pinctrl: Create subdirectory for StarFive drivers Move the StarFive JH7100 pinctrl driver to a new subdirectory in preparation for adding more StarFive pinctrl drivers. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Link: https://lore.kernel.org/r/20220930060819.5320-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3f668365 |
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09-Sep-2022 |
Colin Foster <colin.foster@in-advantage.com> |
pinctrl: ocelot: add help and description information to ocelot pinctrl kconfig Add missed help information and module export name to the Microsemi Ocelot and Jaguar2 SoC. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Link: https://lore.kernel.org/r/20220909153802.3370088-1-colin.foster@in-advantage.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8586466e |
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02-Sep-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: cy8c95x0: Make use of device properties Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Add mod_devicetable.h include. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-13-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e6cbbe42 |
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15-Aug-2022 |
Patrick Rudolph <patrick.rudolph@9elements.com> |
pinctrl: Add Cypress cy8c95x0 support Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and cy8c9560. The GPIO expanders feature a PWM mode, thus add it as pinctrl driver. The chip features multiple drive modes for each pin when configured as output and multiple bias settings when configured as input. Tested all three components and verified that all functionality is fully working. Datasheet: https://www.cypress.com/file/37971/download Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Link: https://lore.kernel.org/r/20220816054917.7893-3-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2f65923c |
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05-Sep-2022 |
Colin Foster <colin.foster@in-advantage.com> |
pinctrl: microchip-sgpio: allow sgpio driver to be used as a module As the commit message suggests, this simply adds the ability to select SGPIO pinctrl as a module. This becomes more practical when the SGPIO hardware exists on an external chip, controlled indirectly by I2C or SPI. This commit enables that level of control. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220905162132.2943088-5-colin.foster@in-advantage.com
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#
4425205e |
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16-Jun-2022 |
Clément Léger <clement.leger@bootlin.com> |
pinctrl: ocelot: allow building as a module Set PINCTRL_OCELOT config option as a tristate and add MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate information. Moreover, switch from builtin_platform_driver() to module_platform_driver(). Signed-off-by: Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
41ef3c1a |
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12-Jul-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
pinctrl: Don't allow PINCTRL_AMD to be a module It was observed that by allowing pinctrl_amd to be loaded later in the boot process that interrupts sent to the GPIO controller early in the boot are not serviced. The kernel treats these as a spurious IRQ and disables the IRQ. This problem was exacerbated because it happened on a system with an encrypted partition so the kernel object was not accesssible for an extended period of time while waiting for a passphrase. To avoid this situation from occurring, stop allowing pinctrl-amd from being built as a module and instead require it to be built-in or disabled. Reported-by: madcatx@atlas.cz Suggested-by: jwrdegoede@fedoraproject.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=216230 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220713175950.964-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
aa74c44b |
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16-Jan-2022 |
Wells Lu <wellslutw@gmail.com> |
pinctrl: Add driver for Sunplus SP7021 Add driver for Sunplus SP7021 SoC. Signed-off-by: Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b124c8bd |
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09-Dec-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: Sort Kconfig and Makefile entries alphabetically Sort Kconfig and Makefile entries alphabetically for better maintenance in the future. While at it fix some style issues, such as: - "Say Y"/"Say yes"/"Say Yes" --> "Say Y" - "pullup/pulldown" --> "pull-up and pull-down" - wrong indentation Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
12422af8 |
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30-Nov-2021 |
Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> |
pinctrl: Add Intel Thunder Bay pinctrl driver About Intel Thunder Bay: ----------------------- Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Thunder Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Thunder Bay SoC. Co-developed-by: Kiran Kumar S <kiran.kumar1.s@intel.com> Signed-off-by: Kiran Kumar S <kiran.kumar1.s@intel.com> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ec648f6b |
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06-Jul-2021 |
Emil Renner Berthing <kernel@esmil.dk> |
pinctrl: starfive: Add pinctrl driver for StarFive SoCs Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which is said to feature only minor changes to these pinctrl/GPIO parts. For each "GPIO" there are two registers for configuring the output and output enable signals which may come from other peripherals. Among these are two special signals that are constant 0 and constant 1 respectively. Controlling the GPIOs from software is done by choosing one of these signals. In other words the same registers are used for both pin muxing and controlling the GPIOs, which makes it easier to combine the pinctrl and GPIO driver in one. I wrote the pinconf and pinmux parts, but the GPIO part of the code is based on the GPIO driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Co-developed-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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#
a0f160ff |
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26-Oct-2021 |
Joey Gouly <joey.gouly@arm.com> |
pinctrl: add pinctrl/GPIO driver for Apple SoCs This driver adds support for the pinctrl / GPIO hardware found on some Apple SoCs. Co-developed-by: Stan Skowronek <stan@corellium.com> Signed-off-by: Stan Skowronek <stan@corellium.com> Signed-off-by: Joey Gouly <joey.gouly@arm.com> Acked-by: Hector Martin <marcan@marcan.st> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f1497303 |
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22-Jul-2021 |
Jiaxun Yang <jiaxun.yang@flygoat.com> |
pinctrl: pistachio: Make it as an option So it will be avilable for generic MIPS kernel. -- Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> v3: Depend on OF as well Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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#
ffd4e739 |
|
06-Aug-2021 |
Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> |
pinctrl: Add Intel Keem Bay pinctrl driver About Intel Keem Bay: ------------------- Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU. Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Keem Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC. Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Reviewed-by: Mark Gross <mgross@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6ceb3c64 |
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20-Jul-2021 |
Jiaxun Yang <jiaxun.yang@flygoat.com> |
pinctrl: pistachio: Make it as an option So it will be avilable for generic MIPS kernel. -- Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> v3: Depend on OF as well Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fa99e701 |
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21-Jun-2021 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
pinctrl: zynqmp: some code cleanups Some minor code cleanups and updates which includes - Mention module name under help in Kconfig. - Remove extra lines and duplicate Pin range checks. - Replace 'return ret' with 'return 0' in success path. - Copyright year update. - use devm_pinctrl_register() instead pinctrl_register() in probe. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8b242ca7 |
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22-Apr-2021 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
pinctrl: Add Xilinx ZynqMP pinctrl driver support Adding pinctrl driver for Xilinx ZynqMP platform. This driver queries pin information from firmware and registers pin control accordingly. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1619080202-31924-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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febb4ee2 |
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16-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: PINCTRL_ROCKCHIP should depend on ARCH_ROCKCHIP The Rockchip GPIO and pin control modules are only present on Rockchip SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the user about this driver when configuring a kernel without Rockchip platform support. Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and automatically selected when needed. By making it tristate and user-selectable, it became visible for everyone. Fixes: be786ac5a6c4bf4e ("pinctrl: rockchip: make driver be tristate module") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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be786ac5 |
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04-Mar-2021 |
Jianqun Xu <jay.xu@rock-chips.com> |
pinctrl: rockchip: make driver be tristate module Make pinctrl-rockchip driver to be tristate module, support to build as a module, this is useful for GKI. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210305003907.1692515-3-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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25fda51c |
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04-Mar-2021 |
Jianqun Xu <jay.xu@rock-chips.com> |
arm64: remove select PINCTRL_ROCKCHIP from ARCH_ROCKCHIP Prepare to make pinctrl driver of rockchip to be module able, this patch remove the select of PINCTRL_ROCKCHIP from ARCH_ROCKCHIP. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210305003907.1692515-2-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d4c34d09 |
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11-Jan-2021 |
Damien Le Moal <damien.lemoal@wdc.com> |
pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver Add the pinctrl-k210.c pinctrl driver for the Canaan Kendryte K210 field programmable IO array (FPIOA) to allow configuring the SoC pin functions. The K210 has 48 programmable pins which can take any of 256 possible functions. This patch is inspired from the k210 pinctrl driver for the u-boot project and contains many direct contributions from Sean Anderson. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC FPIOA DRIVER" with myself listed as maintainer for this driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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4ef82b30 |
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20-Jan-2021 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: remove ste u300 driver The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5817364a |
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20-Jan-2021 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: remove coh901 driver The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c41e02c3 |
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20-Jan-2021 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: remove sirf atlas/prima drivers The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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484c58d6 |
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20-Jan-2021 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: remove zte zx driver The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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be2dc859 |
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09-Dec-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) This adds 'interrupt-controller' features for the signals available on the Microchip SGPIO controller, however only for controller versions on the Sparx5 platform (or later). Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20201209142753.683208-2-lars.povlsen@microchip.com [Select GPIOLIB_IRQCHIP in Kconfig] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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518b466a |
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08-Dec-2020 |
Sergio Paracuellos <sergio.paracuellos@gmail.com> |
pinctrl: ralink: add a pinctrl driver for the rt2880 family These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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0a03658d |
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24-Nov-2020 |
Tiezhu Yang <yangtiezhu@loongson.cn> |
pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will be not built in drivers/base/platform.c and then there exists a build error about undefined reference to "devm_platform_ioremap_resource" in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4, make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1606209423-4742-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
552a9cc0 |
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25-Nov-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
pinctrl: pinctrl-microchip-sgpio: Add OF config dependency The pinctrl-microchip-sgpio driver needs OF support, so add that to Kconfig. Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20201125122014.11237-1-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
7e5ea974 |
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13-Nov-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO (SGPIO) device used in various SoC's. The driver is added as a pinctrl driver, albeit only having just GPIO support currently. The hardware supports other functions that will be added following. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20201113145151.68900-3-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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077365a9 |
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09-Sep-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: Rename sh-pfc to renesas The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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af028ecd |
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23-Aug-2020 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place Renesas related pinctrl CONFIGs are located in many places, which is confusing. This patch collects them into the same place, grouped in a new "Renesas pinctrl drivers" menu. This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com [geert: Update path in MAINTAINERS] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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0662e4a1 |
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05-Sep-2020 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
pinctrl: rockchip: depend on OF The Rockchip pinctrl driver needs to handle information from Devicetree so only makes sense getting compiled on systems with CONFIG_OF enabled. This also fixes a problem found by the "kernel-test-robot" when compiling the driver on test-builds that do not have CONFIG_OF enabled: drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups': >> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration] 2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | pinconf_generic_dump_config drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register': >> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node' 3473 | gc->of_node = bank->of_node; Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a68a7844 |
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09-Sep-2020 |
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> |
pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support Add pinctrl support to Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp> Link: https://lore.kernel.org/r/20200909204336.2558-3-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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e682fcc7 |
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23-May-2020 |
Tiezhu Yang <yangtiezhu@loongson.cn> |
pinctrl: at91-pio4: Add COMPILE_TEST support Add COMPILE_TEST support to the AT91 PIO4 pinctrl driver for better compile testing coverage. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1590234326-2194-2-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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47fa5c97 |
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07-May-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: amd: Add ACPI dependency Currently the AMD pin controller driver supports ACPI platform only. Make the PINCTRL_AMD config symbol depend on ACPI, to avoid asking the user about it when configuring a kernel without ACPI support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113751.24213-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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80691a8a |
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07-May-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: equilibrium: Add architecture dependency The Equilibrium pin controller is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PINCTRL_EQUILIBRIUM config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113626.24026-2-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0f04a817 |
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07-Apr-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: mcp23s08: Split to three parts: core, I²C, SPI Split the driver to three parts: core, I²C, SPI. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200407173849.43628-9-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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56cc3af4 |
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08-Jan-2020 |
Marco Felsch <m.felsch@pengutronix.de> |
pinctrl: da9062: add driver support The DA9062 is a mfd pmic device which supports 5 GPIOs. The GPIOs can be used as input, output or have a special use-case. The patch adds the support for the normal input/output use-case. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/20200108104746.1765-4-m.felsch@pengutronix.de Reviewed-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9e65527a |
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10-Dec-2019 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fixup PIN_CONFIG_OUTPUT config JZ4760 support was added in parallel of the previous patch so this one slipped through. The first SoC to use the new register is the JZ4760 and not the JZ4770, fix it here. Fixes: 7009d046a601 ("pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191210164446.53912-1-paul@crapouillou.net [Folded into OF dependency] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d5a36214 |
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04-Dec-2019 |
Rahul Tanwar <rahul.tanwar@linux.intel.com> |
pinctrl: Modify Kconfig to fix linker error Fix below linker error ld: drivers/pinctrl/pinctrl-equilibrium.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-equilibrium.c:(.text+0xb): undefined reference to `pinconf_generic_dt_node_to_map' Caused by below commit 1948d5c51dba ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") by adding 'depends on OF' in Kconfig driver entry. Reported-by: Randy Dunlap <rdunlap@infradead.org>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/ba937f271d1a2173828a2325990d62cb36d61595.1575514110.git.rahul.tanwar@linux.intel.com Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2635adb4 |
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20-Nov-2019 |
Krzysztof Kozlowski <krzk@kernel.org> |
pinctrl: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306382-32516-1-git-send-email-krzk@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1948d5c5 |
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15-Nov-2019 |
Rahul Tanwar <rahul.tanwar@linux.intel.com> |
pinctrl: Add pinmux & GPIO controller driver for a new SoC Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP which controls pin multiplexing & configuration including GPIO functions selection & GPIO attributes configuration. This IP is not based on & does not have anything in common with Chassis specification. The pinctrl drivers under pinctrl/intel/* are all based upon Chassis spec compliant pinctrl IPs. So this driver doesn't fit & can not use pinctrl framework under pinctrl/intel/* and it requires a separate new driver. Add a new GPIO & pin control framework based driver for this IP. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/33e649758b70490f01724a887c490d5008c7656d.1573797249.git.rahul.tanwar@linux.intel.com Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ec2e0f4f |
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24-May-2019 |
Amelie Delaunay <amelie.delaunay@st.com> |
pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined When CONFIG_GPIO_OF is not defined, struct gpio_chip 'of_node' member does not exist: drivers/pinctrl/pinctrl-stmfx.c: In function 'stmfx_pinctrl_probe': drivers/pinctrl/pinctrl-stmfx.c:652:17: error: 'struct gpio_chip' has no member named 'of_node' pctl->gpio_chip.of_node = np; Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ec8f24b7 |
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19-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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9af2de76 |
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10-May-2019 |
Amelie Delaunay <amelie.delaunay@st.com> |
pinctrl: Kconfig: Fix STMFX GPIO expander Pinctrl/GPIO driver dependencies module_i2c_driver and pinconf_generic_dt_node_to_map_pin are undeclared if CONFIG_I2C and CONFIG_OF are not enabled. Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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1490d9f8 |
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09-May-2019 |
Amelie Delaunay <amelie.delaunay@st.com> |
pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on generic pin config interface to configure the GPIOs. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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8293b3c6 |
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25-Apr-2019 |
Manivannan Sadhasivam <mani@kernel.org> |
pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver Make the BM1880 SoC pinctrl driver depend on COMPILE_TEST to get compiler test coverage and also select this driver by default for ARCH_BITMAIN platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8f3f0246 |
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24-Apr-2019 |
Manivannan Sadhasivam <mani@kernel.org> |
pinctrl: Add pinctrl support for BM1880 SoC Add pinctrl support for Bitmain BM1880 SoC. The driver only handles pinmuxing as the SoC is not capable of handling pinconf. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2dab3dd1 |
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22-Dec-2018 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: ocelot: Add dependency on HAS_IOMEM As usual the build fails on UM Linux because that thing does not have IOMEM. Depend on HAS_IOMEM solves the build problem. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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da801ab5 |
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20-Dec-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
pinctrl: ocelot: add MSCC Jaguar2 support Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning that there are 2 registers instead of one. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b59d0e78 |
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15-Nov-2018 |
Chris Brandt <chris.brandt@renesas.com> |
pinctrl: Add RZ/A2 pin and gpio controller Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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4e53b500 |
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26-Sep-2018 |
Phil Edworthy <phil.edworthy@renesas.com> |
pinctrl: renesas: Renesas RZ/N1 pinctrl driver This provides a pinctrl driver for the Renesas RZ/N1 device family. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
635c20a1 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Drop dependency on MACH_INGENIC Depending on MACH_INGENIC prevent us from creating a generic kernel that works on more than one MIPS board. Instead, we just depend on MIPS being set. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e72394e2 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Merge GPIO functionality Merge the code of the gpio-ingenic driver into the pinctrl-ingenic driver. The reason behind this, is that the same hardware block handles both pin config / muxing and GPIO. ingenic_gpio_probe() have been marked as __init, but for the most part, the code is the exact same as what it was in the gpio-ingenic driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3b588e43 |
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07-Aug-2018 |
Tomer Maimon <tmaimon77@gmail.com> |
pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [Add back select GPIO_GENERIC] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
be36abb7 |
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25-Jul-2018 |
Quentin Schulz <quentin.schulz@bootlin.com> |
pinctrl: ocelot: add support for interrupt controller This GPIO controller can serve as an interrupt controller as well on the GPIOs it handles. An interrupt is generated whenever a GPIO line changes and the interrupt for this GPIO line is enabled. This means that both the changes from low to high and high to low generate an interrupt. For some use cases, it makes sense to ignore the high to low change and not generate an interrupt. Such a use case is a line that is hold in a level high/low manner until the event holding the line gets acked. This can be achieved by making sure the interrupt on the GPIO controller side gets acked and masked only after the line gets hold in its default state, this is what's done with the fasteoi functions. Only IRQ_TYPE_EDGE_BOTH and IRQ_TYPE_LEVEL_HIGH are supported for now. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6ff45566 |
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15-Feb-2018 |
Jan Kundrát <jan.kundrat@cesnet.cz> |
pinctrl: mcp23s08: Kconfig: update to reflect supported features Commit d8f4494e70ae removed comments which described this limitation. The code supported interrupts even before. Also add some spacing so that the chip IDs are a bit more readable. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Reviewed-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
218d72a7 |
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21-May-2018 |
Richard Fitzgerald <rf@opensource.cirrus.com> |
pinctrl: madera: Add driver for Cirrus Logic Madera codecs These codecs have a variable number of I/O lines each of which is individually selectable to a wide range of possible functions. The functionality is slightly different from the traditional muxed GPIO since most of the functions can be mapped to any pin (and even the same function to multiple pins). Most pins have a dedicated "alternate" function that is only available on that pin. The alternate functions are usually a group of signals, though it is not always necessary to enable the full group, depending on the alternate function and how it is to be used. The mapping between alternate functions and GPIO pins varies between codecs depending on the number of alternate functions and available pins. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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#
2242ddfb |
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04-Apr-2018 |
Manivannan Sadhasivam <mani@kernel.org> |
pinctrl: actions: Add Actions S900 pinctrl driver Add pinctrl driver for Actions Semi S900 SoC. The driver supports pinctrl, pinmux and pinconf functionalities through a range of registers common to both gpio driver and pinctrl driver. Pinmux functionality is available only for the pin groups while the pinconf functionality is available for both pin groups and individual pins. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f59b2dc2 |
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09-Mar-2018 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: remove adi2/blackfin drivers The blackfin architecture is getting removed, so these are now obsolete. Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
4a7cba71 |
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21-Feb-2018 |
James Hogan <jhogan@kernel.org> |
pinctrl: Drop TZ1090 drivers Now that arch/metag/ has been removed, along with TZ1090 SoC support, remove the TZ1090 pinctrl drivers. They are of no value without the architecture and SoC platform code. Signed-off-by: James Hogan <jhogan@kernel.org> Cc: linux-gpio@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ce8dc094 |
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05-Jan-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
pinctrl: Add Microsemi Ocelot SoC driver The Microsemi Ocelot SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing and the GPIOs. There is currently no support for interrupts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
971f1b38 |
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14-Dec-2017 |
Quentin Schulz <quentin.schulz@free-electrons.com> |
pinctrl: axp209: add missing Kconfig dependencies This fixes some compilation issues. GENERIC_PINCONF and OF at least for pinconf_generic_dt_*, PINMUX at least for pinmux_ops and GPIOLIB for at least gpio_chip. Fixes: 23f75d7dfa92 ("pinctrl: axp209: add pinctrl features") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
449317a8 |
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05-Dec-2017 |
Quentin Schulz <quentin.schulz@free-electrons.com> |
pinctrl: move gpio-axp209 to pinctrl To prepare the driver for the upcoming pinctrl features, move the GPIO driver AXP209 from GPIO to pinctrl subsystem. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fd35b202 |
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13-Nov-2017 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: Add some depends on HAS_IOMEM Some compilation fallout from UM Linux (which does not have IOMEM) makes it necessary to depend on HAS_IOMEM for drivers that doesn't have other factors restricting their selection. Cc: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Reported-by: R. Daneel Olivaw <kbuild-all@01.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1c5b7f3c |
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28-Oct-2017 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: gemini: Use generic DT parser We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1c363531 |
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11-Oct-2017 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: adi2: Fix Kconfig build problem The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(®s->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(®s->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
277d14eb |
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12-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: separate soc drivers When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e2a021d4 |
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10-Oct-2017 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: Do not depend in GPIOLIB, select it Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d219b924 |
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05-Oct-2017 |
Phil Reid <preid@electromag.com.au> |
pinctrl: change Kconfig PINCTRL variable to a menuconfig This allows PINCTRL to be selected manually to allow enabling of the mcp23s08 i2c/spi gpio driver. Which is not platform specific. Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
83b31c2a |
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26-Sep-2017 |
Petr Mladek <pmladek@suse.com> |
pinctrl/amd: Fix build dependency on pinmux code The commit 79d2c8bede2c93f943 ("pinctrl/amd: save pin registers over suspend/resume") caused the following compilation errors: drivers/pinctrl/pinctrl-amd.c: In function ‘amd_gpio_should_save’: drivers/pinctrl/pinctrl-amd.c:741:8: error: ‘const struct pin_desc’ has no member named ‘mux_owner’ if (pd->mux_owner || pd->gpio_owner || ^ drivers/pinctrl/pinctrl-amd.c:741:25: error: ‘const struct pin_desc’ has no member named ‘gpio_owner’ if (pd->mux_owner || pd->gpio_owner || We need to enable CONFIG_PINMUX for this driver as well. Cc: stable@vger.kernel.org Fixes: 79d2c8bede2c93f943 ("pinctrl/amd: save pin registers over suspend/resume") Signed-off-by: Petr Mladek <pmladek@suse.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
41d32cfc |
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17-Aug-2017 |
Baolin Wang <baolin.wang@spreadtrum.com> |
pinctrl: sprd: Add Spreadtrum pin control driver This patch adds the pin control driver for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ea479996 |
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20-Aug-2017 |
Joseph Chen <chenjh@rock-chips.com> |
pinctrl: Add pinctrl driver for the RK805 PMIC RK805 is one of Rockchip PMICs family, it has 2 output only GPIOs. This driver is also designed for other Rockchip PMICs to expend. Different PMIC maybe have different pin features, for example, RK816 has one pin which can be used for TS or GPIO(input/out). The mainly difference between PMICs pins are pinmux, direction and output value, that is 'struct rk805_pin_config'. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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#
06351d13 |
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05-Aug-2017 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: add a Gemini SoC pin controller This adds a pin control (only multiplexing) driver for the Gemini SoC so we can sort out this complex platform in an orderly manner. This driver will detect the chip/package version as SL3512 or SL3516 (also known as CS3512 and CS3516 etc) and register the apropriate pin set. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5a49b644 |
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22-Jun-2017 |
Jacopo Mondi <jacopo+renesas@jmondi.org> |
pinctrl: Renesas RZ/A1 pin and gpio controller Add combined gpio and pin controller driver for Renesas RZ/A1 r7s72100 SoC. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
adeac775 |
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30-May-2017 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: mcp23s08: improve I2C Kconfig dependency With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver, which then results in a link failure: drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0': :(.text+0x7910): undefined reference to `__devm_regmap_init_i2c' drivers/pinctrl/built-in.o: In function `mcp23s08_init': :(.init.text+0x110): undefined reference to `i2c_register_driver' drivers/pinctrl/built-in.o: In function `mcp23s08_exit': :(.exit.text+0x3c): undefined reference to `i2c_del_driver' To avoid the problem, this adds another dependency on I2C that enforces mcp23s08 to be a loadable module whenever the I2C core is a module. Fixes: 64ac43e6fa28 ("gpio: mcp23s08: move to pinctrl") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c504985e |
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29-May-2017 |
Linus Walleij <linus.walleij@linaro.org> |
gpio/pinctrl: ingenic: depend on OF Fix compile errors due to missing OF. Cc: Paul Cercueil <paul@crapouillou.net> Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
25ca1cea |
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15-May-2017 |
Sebastian Reichel <sre@kernel.org> |
pinctrl: mcp23s08: drop OF_GPIO dependency The driver compiles & works perfectly fine without OF_GPIO on x86, so lets drop the dependency. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
82039d24 |
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15-May-2017 |
Sebastian Reichel <sre@kernel.org> |
pinctrl: mcp23s08: add pinconf support mcp23xxx device have configurable 100k pullup resistors. This adds support for enabling them using pinctrl's pinconf interface. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
64ac43e6 |
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15-May-2017 |
Sebastian Reichel <sre@kernel.org> |
gpio: mcp23s08: move to pinctrl This moves the mcp23s08 driver from gpio to pinctrl. Actual pinctrl support for configuration of the pull-up resistors follows in its own patch. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b5c23aa4 |
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12-May-2017 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs This driver handles pin configuration and pin muxing for the JZ4740 and JZ4780 SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
cbff0c4d |
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24-Apr-2017 |
Shawn Guo <shawn.guo@linaro.org> |
pinctrl: add ZTE ZX pinctrl driver support The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of a main controller and an auxiliary one. For example, on ZX296718 SoC, the main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both controllers work together to control pin multiplexing and configuration. For most of pins, the pinmux function is controlled by main controller only, and this type of pins are meant by term 'TOP pins'. For other pins, the pinmux is controlled by both main and auxiliary controllers, as the available multiplexing functions for the pin spread in both controllers. This type of pins are called 'AON pins'. Though pinmux implementation is quite different, pinconf is same for both types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG on ZX296718. The patch adds the ZTE ZX core pinctrl driver to support this hybrid pin controller as well as ZX296718 SoC specific pin data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
00df0582 |
|
03-Apr-2017 |
Jesper Nilsson <jesper.nilsson@axis.com> |
pinctrl: Add pincontrol driver for ARTPEC-6 SoC Add pinctrl driver support for the Axis ARTPEC-6 SoC. There are only some pins that actually have different functions available, but all can control bias (pull-up/-down) and drive strength. Code originally written by Chris Paterson. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
003910eb |
|
05-Jan-2017 |
Nishanth Menon <nm@ti.com> |
pinctrl: Introduce TI IOdelay configuration driver SoC family such as DRA7 family of processors have, in addition to the regular muxing of pins (as done by pinctrl-single), a separate hardware module called IODelay which is also expected to be configured. The "IODelay" module has it's own register space that is independent of the control module and the padconf register area. With recent changes to the pinctrl framework, we can now support this hardware with a reasonably minimal driver by using #pinctrl-cells, GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay reconfiguration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do as little of muxing as absolutely necessary without I/O isolation (which can only be done in initial stages of bootloader). NOTE: with the system wide I/O isolation scheme present in DRA7 SoC family, it is not reasonable to do stop all I/O operations for every such pad configuration scheme. So, we will let it glitch when used in this mode. Even with the above limitation, certain functionality such as MMC has mandatory need for IODelay reconfiguration requirements, depending on speed of transfer. In these cases, with careful examination of usecase involved, the expected glitch can be controlled such that it does not impact functionality. In short, IODelay module support as a padconf driver being introduced here is not expected to do SoC wide I/O Isolation and is meant for a limited subset of IODelay configuration requirements that need to be dynamic and whose glitchy behavior will not cause functionality failure for that interface. IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared to 0x0 at all times, even when configuring Manual IO Timing Modes. This is done by eliminating the LOCK_BIT=1 setting from Step of the Manual IO timing Mode configuration procedure. This option leaves the CFG_* registers unprotected from unintended writes to the CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured. This approach is taken to allow for a generic driver to exist in kernel world that has to be used carefully in required usecases. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [tony@atomide.com: updated to use generic pinctrl functions, added binding documentation, updated comments] Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
571aec4d |
|
27-Dec-2016 |
Tony Lindgren <tony@atomide.com> |
pinctrl: single: Use generic pinmux helpers for managing functions We can now drop the driver specific code for managing functions. Signed-off-by: Tony Lindgren <tony@atomide.com> [Replaces GENERIC_PINMUX with GENERIC_PINMUX_FUNCTIONS] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
caeb774e |
|
27-Dec-2016 |
Tony Lindgren <tony@atomide.com> |
pinctrl: single: Use generic pinctrl helpers for managing groups We can now drop the driver specific code for managing groups. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a76edc89 |
|
27-Dec-2016 |
Tony Lindgren <tony@atomide.com> |
pinctrl: core: Add generic pinctrl functions for managing groups We can add generic helpers for function handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: Tony Lindgren <tony@atomide.com> [Renamed the Kconfig item and moved things around] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c033a718 |
|
30-Dec-2016 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: stricten up generic group code Rename the symbol PINCTRL_GENERIC to PINCTRL_GENERIC_GROUPS since it all pertains to groups. Replace everywhere. ifdef out the radix tree and the struct when not using the generic groups. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c7059c5a |
|
27-Dec-2016 |
Tony Lindgren <tony@atomide.com> |
pinctrl: core: Add generic pinctrl functions for managing groups We can add generic helpers for pin group handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
1ff91f0a |
|
28-Nov-2016 |
David Lechner <david@lechnology.com> |
pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0db0f26c |
|
07-Nov-2016 |
Andrey Smirnov <andrew.smirnov@gmail.com> |
pinctrl-sx150x: Convert driver to use regmap API To allow for future code simplification Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
24d6a91c |
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28-Oct-2016 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: max77620: add OF dependency Drivers using pinconf_generic_params tables cannot be built with CONFIG_OF disabled: drivers/pinctrl/pinctrl-max77620.c:53:44: error: array type has incomplete element type ‘struct pinconf_generic_params’ drivers/pinctrl/pinctrl-max77620.c:55:3: error: field name not in record or union initializer drivers/pinctrl/pinctrl-max77620.c:55:3: note: (near initialization for ‘max77620_cfg_params’) drivers/pinctrl/pinctrl-max77620.c:56:3: error: field name not in record or union initializer This adds a dependency for max77620 to disallow that configuration. Alternatively, we could rework the pinctrl infrastructure to make the configuration valid for compile-testing. Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Lee Jones <lee.jones@linaro.org> Fixes: 453943dc8f45 ("mfd: Enable compile testing for max77620 and max77686") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9e80f906 |
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21-Oct-2016 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: Add SX150X GPIO Extender Pinctrl Driver Since the I2C sx150x GPIO expander driver uses platform_data to manage the pins configurations, rewrite the driver as a pinctrl driver using pinconf to get/set pin configurations from DT or debugfs. The pinctrl driver is functionnally equivalent as the gpio-only driver and can use DT for pinconf. The platform_data confirmation is dropped. This patchset removed the gpio-only driver and selects the Pinctrl driver config instead. This patchset also migrates the gpio dt-bindings to pinctrl and add the pinctrl optional properties. The driver was tested with a SX1509 device on a BeagleBone black with interrupt support and on an X86_64 machine over an I2C to USB converter. This is a fixed version that builds and runs on non-OF platforms and on arm based OF. The GPIO version is removed and the bindings are also moved to the pinctrl bindings. Changes since v2 - rebased on v4.9-rc1 - removed MODULE_DEVICE_TABLE as in upstream bb411e771b0e ("gpio: sx150x: fix implicit assumption module.h is present") Changes since v1 - Fix Kconfig descriptions on pinctrl and gpio - Fix Kconfig dependency - Remove oscio support for non-789 devices - correct typo in dt bindings - remove probe reset for non-789 devices Changes since RFC - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms - No more rely on OF_GPIO config - Moved and enhanced bindings to pinctrl bindings - Removed gpio-sx150x.c - Temporary select PINCTRL_SX150X when GPIO_SX150X - Temporary mark GPIO_SX150X as deprecated Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Peter Rosin <peda@axentia.se> Acked-by: Rob Herring <robh@kernel.org> ested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4d3d0e42 |
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30-Aug-2016 |
Andrew Jeffery <andrew@aj.id.au> |
pinctrl: Add core support for Aspeed SoCs The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9385f35d |
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13-Jun-2016 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
pinctrl: as3722: convert PINCTRL_AS3722 from bool to tristate The Kconfig currently controlling compilation of this code is: config PINCTRL_AS3722 bool "Pinctrl and GPIO driver for ams AS3722 PMIC" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
767b8ce3 |
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13-Jun-2016 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
pinctrl: palmas: convert PINCTRL_PALMAS from bool to tristate The Kconfig currently controlling compilation of this code is: config PINCTRL_PALMAS bool "Pinctrl driver for the PALMAS Series MFD devices" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
79f28b9f |
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13-Jun-2016 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: max77620: select PINMUX The recently added max77620 driver fails to build when CONFIG_PINMUX is not set: pinctrl/pinctrl-max77620.c:272:21: error: variable 'max77620_pinmux_ops' has initializer but incomplete type static const struct pinmux_ops max77620_pinmux_ops = { ^~~~~~~~~~ pinctrl/pinctrl-max77620.c:273:2: error: unknown field 'get_functions_count' specified in initializer This adds the Kconfig 'select' statement that was clearly meant to be there and is used in all other pinmux drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2df723d4 |
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12-May-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024 MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins which also act as the special function in alternate mode. Also there is configuration like push-pull, open drain, FPS timing etc for these pins. Add pin control driver to configure these parameters through pin control APIs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
611dac1e |
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11-May-2016 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
337ea0fb |
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10-Feb-2016 |
Jean Delvare <jdelvare@suse.de> |
pinctrl: Turn AMD support to tristate The pinctrl-amd driver builds just fine as a module so give users this option. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2ba384e6 |
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01-Feb-2016 |
Joshua Henderson <joshua.henderson@microchip.com> |
pinctrl: pinctrl-pic32: Add PIC32 pin control driver Add a driver for the pin controller present on the Microchip PIC32 including the specific variant PIC32MZDA. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
25cbac77 |
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23-Jan-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: tegra: move Tegra pinctrl drivers to sub-directory Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
aceb16dc |
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14-Jan-2016 |
Maxime Coquelin <mcoquelin.stm32@gmail.com> |
pinctrl: Add STM32 MCUs support This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4b15ec9d |
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21-Nov-2015 |
Robert Jarzmik <robert.jarzmik@free.fr> |
pinctrl: activate pxa architecture As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
485dba27 |
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30-Nov-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: fix a typo in Kconfig Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
932cb839 |
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04-Nov-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: remove redundant if conditional from Kconfig The whole menu is guarded by menu "Pin controllers" depends on PINCTRL ... endmenu The if conditional outside of it is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
77618084 |
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16-Sep-2015 |
Ludovic Desroches <ludovic.desroches@atmel.com> |
pinctrl: introduce driver for Atmel PIO4 controller Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2 chip family. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
38b0e507 |
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05-May-2015 |
Baruch Siach <baruch@tkos.co.il> |
pinctrl: driver for Conexant Digicolor CX92755 pin mapping This adds pinctrl and gpio driver to the CX92755 SoC "General Purpose Pin Mapping" hardware block. The CX92755 is one SoC from the Conexant Digicolor series. Pin mapping hardware supports configuring pins as either GPIO, or up to 3 other "client select" functions. This driver adds support for pin muxing using the generic device tree binding, and a basic gpiolib driver for the GPIO functionality. This driver does not currently support GPIO interrupts, and pad configuration. v2: * Address review comments for Linus Walleij: - Add a pointer to pinctrl_desc in struct dc_pinmap - Drop the now redundant pinctrl_pin_desc field - Adapt dc_get_group_{name,pins} to these changes, and add a comment explaining the 1-to-1 pin-groups relation * Staticise dc_pmxops * Protect the GP_CLIENTSEL clct parameter with parenthesis Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6e908892 |
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13-Jul-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: UniPhier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Changes in v2: - drop vogus THIS_MODULE because this file is always built-in - drop vogus "include <linux/module.h> because this file is always built-in Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f9367793 |
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18-May-2015 |
Wei Chen <Wei.Chen@csr.com> |
pinctrl: sirf: add sirf atlas7 pinctrl and gpio support The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
cefc03e5 |
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06-May-2015 |
Andrew Bresticker <abrestic@chromium.org> |
pinctrl: Add Pistachio SoC pin control driver Add a driver for the pin controller present on the IMG Pistachio SoC. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Changes from v4: - Switched to using gpiochip_add_pin_range(). - Fixed up Kconfig entry. Changes from v3: - Addressed review comments from Ezequiel. Changes from v2: - Removed module stuff which would be compiled out. Changes from v1: - Addressed review comments from Linus. - Changed compatible string to "img,pistachio-system-pinctrl". - Look for GPIO sub-nodes by name. - A couple of bug fixes. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Kevin Cernekee <cernekee@chromium.org> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2f77ac93 |
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27-Apr-2015 |
Joachim Eastwood <manabian@gmail.com> |
pinctrl: add lpc18xx pinctrl driver Pinctrl driver for the System Control Unit (SCU) found on NXP LPC18xx/43xx devices. Driver uses the generic pinctrl DT bindings for multiplexing and property settings. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b99e6fb8 |
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15-Apr-2015 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: fix allmodconfig noise There was some mess in the dependencies in the pinctrl Kconfig for compile tests under allmodconfig. Mea Culpa. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dbad75dd |
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10-Mar-2015 |
Ken Xue <Ken.Xue@amd.com> |
pinctrl: add AMD GPIO driver support. KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a6df410d |
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20-Jan-2015 |
Hongzhou Yang <hongzhou.yang@mediatek.com> |
pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135. The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b17f2f9b |
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04-Mar-2015 |
Ray Jui <rjui@broadcom.com> |
pinctrl: bcm: consolidate Broadcom pinctrl drivers Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9184f756 |
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24-Feb-2015 |
Stephen Warren <swarren@nvidia.com> |
pinctrl: tegra: add a driver for Tegra210 Tegra210's pinmux supports a different set of pins/options than earlier SoCs, so requires its own driver (well, table of pin-specific data). Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6ac73095 |
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17-Jan-2015 |
Beniamino Galvani <b.galvani@gmail.com> |
pinctrl: add driver for Amlogic Meson SoCs This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a17272a4 |
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11-Jan-2015 |
Barry Song <Baohua.Song@csr.com> |
pinctrl: sirf: drop marco support marco chip has been dropped, clear its support. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
add958ce |
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09-Jan-2015 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
pinctrl: Add driver for Zynq This adds a pin-control driver for Zynq. Changes since v2: - driver-specific DT properties are passed to the core in two arrays, one for the actual DT parsing one for the debugfs representation. Issue a compiler warning when the number of entries is not the same for both arrays. Changes since v1: - fix EMIO_SD1_CD pin name - add USB to pinmux options changes since RFCv2: - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is present in DT but no driver available. - add #defines to get rid of magical constants - add commas at end of initializers - separate changes in mach-zynq in separate patch - add driver specific io-standard DT property - refactored pinconf set function to not require arguments for argument-less properties - squash other patches in - support for IO-standard property - support for low-power mode property - migration to pinconf_generic_dt_node_to_map_all() - use newly created infrastructure to add pass driver-specific DT params to pinconf-generic changes since RFC: - use syscon/regmap to access registers in SLCR space - rebase to 3.18: rename enable -> set_mux - add kernel-doc - support pinconf - supported attributes - pin-bias: pull up, tristate, disable - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display argument Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5fae8b86 |
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24-Oct-2014 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
pinctrl: Move Intel Baytrail pinctrl driver under intel directory We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e4742d57 |
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24-Sep-2014 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: bcm281xx: make Kconfig dependency more strict This driver is only useful on BCM281xx, so let the driver depend on ARCH_BCM_MOBILE but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
edad3b2a |
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03-Sep-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: imx/mxs: move freescale drivers to subdir This moves all the Freescale-related drivers (i.MX and MXS) to its own subdirectory to clear the view. Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Anson Huang <b20788@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Denis Carikli <denis@eukrea.com> Cc: Markus Pargmann <mpa@pengutronix.de> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4f671cb2 |
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26-Jul-2014 |
Alexander Shiyan <shc_work@mail.ru> |
pinctrl: Add i.MX21 pincontrol driver This patch adds pincontrol driver for Freescale i.MX21 SOCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
e1ee5c57 |
|
25-Jul-2014 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
pinctrl: baytrail: Convert to use gpiolib irqchip Instead of open-coding irqchip handling in the driver we can take advantage of the new irqchip helpers provided by the gpiolib core. While doing this we also make sure that we call gpiochip_irqchip_add() after the gpiochip itself is registered as required. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3a198059 |
|
11-Jul-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: nomadik: move all Nomadik drivers to subdir We have a bunch of Nomadik family pin control drivers, so let's move them into their own subdirectory. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dc0a3938 |
|
19-Jun-2014 |
Thierry Reding <treding@nvidia.com> |
pinctrl: Add NVIDIA Tegra XUSB pad controller support The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads that lanes can be assigned to in order to support a variety of interface options: USB 2.0, USB 3.0, PCIe and SATA. In addition to the pin controller used to assign lanes to pads two PHYs are exposed to allow the bricks for PCIe and SATA to be powered up and down by PCIe and SATA drivers. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
ebe629a3 |
|
10-Jul-2014 |
Sachin Kamat <sachin.kamat@samsung.com> |
pinctrl: samsung: Group all drivers in a sub-dir Group all pin control drivers of Samsung platform together in a sub-directory for easy maintenance. Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
69b78b8d |
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09-Jul-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: msm: move all qualcomm drivers to subdir We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
14d40ff8 |
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08-Jul-2014 |
Bjorn Andersson <bjorn.andersson@sonymobile.com> |
pinctrl: msm: Add msm8960 definitions Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4877e51e |
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03-Jun-2014 |
Alexander Shiyan <shc_work@mail.ru> |
pinctrl: Add i.MX1 pincontrol driver This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
244e95a7 |
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03-Jun-2014 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONF These symbols are supposed to be selected by the drivers actually needing them. The only situation where it would make sense to enable them without a driver selecting them is when an out-of-tree pinctrl driver is used or for compile testing. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2cc140fe |
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12-May-2014 |
Anson Huang <b20788@freescale.com> |
pinctrl: add pinctrl driver for imx6sx Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
cdcb0ab6 |
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29-Apr-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: msm: switch to using generic GPIO irqchip helpers This switches the Qualcomm MSM pin control driver over to using the generic GPIO irqchip helpers. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3de68d33 |
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19-May-2014 |
Antoine Tenart <atenart@kernel.org> |
pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
751a99ab |
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05-May-2014 |
Heiko Stübner <heiko@sntech.de> |
pinctrl: rockchip: use regmaps instead of raw mappings This allows us to use syscons in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5f910777 |
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18-Apr-2014 |
Maxime Ripard <mripard@kernel.org> |
pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
7420d2d0 |
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15-Apr-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: sirf: switch driver to use gpiolib irqchip helpers This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b4da6573 |
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14-Apr-2014 |
Andy Gross <agross@codeaurora.org> |
pinctrl: qcom: Add definitions for IPQ8064 This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
80cc3732 |
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15-Apr-2014 |
Alexander Stein <alexanders83@web.de> |
pinctrl/at91: convert driver to use gpiolib irqchip This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fb95a94b |
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01-Apr-2014 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: msm8x74: make Kconfig dependency more strict This driver is only useful on MSM8x74, so let the driver depend on ARCH_QCOM but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e2c802be |
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31-Mar-2014 |
Bjorn Andersson <bjorn.andersson@sonymobile.com> |
pinctrl: msm: Add definitions for the APQ8064 platform This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm APQ8064 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
130cbe30 |
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08-Apr-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: st: use gpiolib irqchip helpers This lets the gpiolib core handle the irqchip set-up and chained IRQ on the primary (behind the mux) IRQ chip in the st pinctrl driver. Default irq type is set to level low at irqchip add time. The v1 was sent by Linus (https://lkml.org/lkml/2014/4/4/287). Two changes were necessary to make it to work properly on STiH416: 1 - dev reference was not passed to the gpio_chip struct, causing a panic. 2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as default type, which caused lot of warnings at init time. I choose IRQ_TYPE_LEVEL_LOW as default. Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
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#
7418b5cc |
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02-Apr-2014 |
Sherman Yin <syin@broadcom.com> |
pinctrl: Rename Broadcom Capri pinctrl driver To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl driver and its related CONFIG option are renamed to bcm281xx. Devicetree compatible string and binding documentation use "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
523dcce7 |
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25-Mar-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: coh901: convert driver to use gpiolib irqchip This converts the COH901 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e0bc34a3 |
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25-Mar-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: nomadik: convert driver to use gpiolib irqchip This converts the Nomadik pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5f2449d0 |
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06-Mar-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
pinctrl: msm: Drop OF_IRQ dependency This driver doesn't rely on any functionality living in drivers/of/irq.c to compile. Drop this dependency. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5ba34160 |
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23-Feb-2014 |
Josh Cartwright <joshc@codeaurora.org> |
pinctrl: msm: make PINCTRL_MSM bool instead of tristate Modular builds of pinctrl-msm break due to handle_bad_irq being unexported for module use. For now, make PINCTRL_MSM 'bool'. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fe0ec0ee |
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16-Jan-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: capri: add dependency on OF As this driver is using pinconf_generic_dt_node_to_map_pin() it needs to depend on OF so as not to cause build problems on archs that do not support OF. Cc: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
54b1aa5a |
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20-Dec-2013 |
Sherman Yin <syin@broadcom.com> |
ARM: pinctrl: Add Broadcom Capri pinctrl driver Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig - make use of regmap - change CAPRI_PIN_UPDATE from macro to inline function. - Handle pull-up strength arg in Ohm instead of enum v3: Re-work driver to be based on generic pin config. Moved config selection from Kconfig to bcm_defconfig. v2: Use hyphens instead of underscore in DT property names. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
376f413a |
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14-Dec-2013 |
Bjorn Andersson <bjorn.andersson@sonymobile.com> |
pinctrl: msm: Update Kconfig for PINCTRL_MSM8X74 Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix build errors from i386-randconfig. Also add help text and make the entries tristate, while touching these entries. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> [Rebased on top of pin control development branch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1a16bee6 |
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09-Dec-2013 |
Ashwini Ghuge <aghuge@nvidia.com> |
pinctrl: tegra: add pinmux controller driver for Tegra124 This adds a driver for the Tegra124 pinmux, and required parameterization data for Tegra124. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra124-pinmux". Originally written by Ashwini Gguhe. Thierry: - Cleanups in patches. ldewangan: - Fix some entries for groups. - Fix MUX enums and group sequence. Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> CC: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0a7c0e0c |
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09-Dec-2013 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: make the MSM SoC driver depend on OF We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
18334c8e |
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09-Dec-2013 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: make the MSM SoC driver depend on OF We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ChangeLog v2->v3: - Total failure with older approaches: what we need to do is have the *SoC subdriver* depend on OF and OF_IRQ. This is because the placeholder bool PINCTRL_MSM cannot cascade its dependencies when a subdriver selects it, Kconfig is smart but not that smart. ChangeLog v1->v2: - OK so "depends on OF" did not work here let's try to simply select OF and OF_IRQ for this then? It's one of those "warning: (PINCTRL_MSM8X74) selects PINCTRL_MSM which has unmet direct dependencies (PINCTRL && OF)" that I simply cannot find my way out of :-/
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#
55aaf834 |
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05-Dec-2013 |
Bjorn Andersson <bjorn.andersson@sonymobile.com> |
pinctrl: Add msm8x74 configuration Add initial definition of parameters for pinctrl-msm for the msm8x74 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f365be09 |
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05-Dec-2013 |
Bjorn Andersson <bjorn.andersson@sonymobile.com> |
pinctrl: Add Qualcomm TLMM driver This adds a pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b4a87c9b |
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06-Nov-2013 |
Denis Carikli <denis@eukrea.com> |
pinctrl: pinctrl-imx: add imx25 pinctrl driver This is mostly cut and paste from the imx35 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx25.h. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Eric Bénard <eric@eukrea.com> Signed-off-by: Denis Carikli <denis@eukrea.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b9f2f2ec |
|
16-Nov-2013 |
Shawn Guo <shawn.guo@linaro.org> |
pinctrl: imx: drop redundant OF dependency The IMX/MXC selects USE_OF at architecture level, so the OF dependency at individual SoC pinctrl driver level can just be dropped. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9da83120 |
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05-Nov-2013 |
Greg Ungerer <gerg@uclinux.org> |
pinctrl: imx50: add pinctrl support code for the IMX50 SoC Add code to support the specific pin arrangements of the Freescale IMX50 SoC. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e16dbf60 |
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29-Oct-2013 |
Markus Pargmann <mpa@pengutronix.de> |
pinctrl: imx27: imx27 pincontrol driver imx27 pincontrol driver using the imx1 core driver. The DT bindings are similar to other imx pincontrol drivers. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
30612cd9 |
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28-Oct-2013 |
Markus Pargmann <mpa@pengutronix.de> |
pinctrl: imx1 core driver Core driver for register formats of imx1/imx21/imx27 processors. The pins of those processors are grouped into ports. Each port has 32 pins. The pins mux configuration is controlled by registers with 1 or 2 bit per pin, depending on the specific control register. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5aad0db1 |
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15-Oct-2013 |
Christian Ruppert <christian.ruppert@abilis.com> |
pinctrl: add TB10x pin control driver The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs. Used to control the pinmux and is a prerequisite for the GPIO driver. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c8ce8782 |
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02-Oct-2013 |
Laxman Dewangan <ldewangan@nvidia.com> |
pincntrl: add support for ams AS3722 pin control driver The AS3722 is a compact system PMU suitable for mobile phones, tablets etc. Add a driver to support accessing the GPIO, pinmux and pin configuration of 8 GPIO pins found on the ams AS3722 through pin control driver and gpiolib. The driver will register itself as the pincontrol driver and gpio driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9d7278d0 |
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22-Sep-2013 |
Sonic Zhang <sonic.zhang@analog.com> |
pinctrl: pinctrl-adi2: Add dependency to arch BLACKFIN in Kconfig. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e9a03add |
|
03-Sep-2013 |
Sonic Zhang <sonic.zhang@analog.com> |
pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x. The new ADI GPIO2 controller was introduced since the BF548 and BF60x processors. It differs a lot from the old one on BF5xx processors. So, create a pinctrl driver under the pinctrl framework. - Define gpio ports and pin interrupt controllers as individual platform devices. - Register a pinctrl driver for the whole GPIO ports and pin interrupt devices. - Probe pint devices before port devices. Put device instances into the global gpio and pint lists. - Define peripheral, irq and gpio reservation bit masks for each gpio port as runtime resources. - Save and restore gpio port and pint status MMRs in syscore PM functions. - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data in pin controller probe function. Get the pin groups and functions via the soc data reference. - Call gpiochip_add_pin_range() in gpio device probe function to register range cross reference between gpio device and pin control device. - Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by container_of() and find adi_pinctrl by pin control device name. - Handle peripheral and gpio requests in pinctrl operation functions. - Demux gpio IRQs via the irq_domain created by each GPIO port. v2-changes: - Remove unlinke() directive. v3-changes: - Rename struct adi_pmx to adi_pinctrl. - Fix the comments of struct gpio_pint. - Remove unused pin_base in struct gpio_port. - Change pint_assign into bool type. - Add comments about the relationship between pint device and port device to the driver header. - Use BIT macro to shift bit. - Remove all bitmap reservation help functions. Inline reservation functions into the actual code. - Remove gpio and offset mutual reference help functions. - Remove all help functions to find gpio_port and adi_pinctrl structs. Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by container_of() and find adi_pinctrl by pin control device name. - Pass bool type usage variable to port_setup help function. - Separate long bit operations into several lines and add comments. - Use debugfs to output all GPIO request information. - Avoid to set drvdata to NULL - Add explanation to function adi_gpio_init_int() - Call gpiochip_add_pin_range() in gpio device probe function to register range cross reference between gpio device and pin control device. - Remove the reference to pin control device from the gpio_port struct. Remove the reference list to gpio device from the adi_pinctrl struct. Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through the gpio list to do power suspend and resume operations. - Remove the global GPIO base from struct adi_pinctrl, define pin base in the platform data for each GPIO port device. - Initialize adi_pinctrl_setup in arch_initcall(). - print the status of triggers, whether it is in GPIO mode, if it is flagged to be used as IRQ, etc in adi_pin_dbg_show(). - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data in pin controller probe function. Get the pin groups and functions via the soc data reference. v4-changes: - remove useless system_state checking. - replace dev_err with dev_warn in both irq and gpio pin cases. - comment on relationship between irq type and invert operation. - It is not necessary to check the reservation mode of the requested pin in IRQ chip operation. Remove the reservation map. - Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2 driver specific debugfs output. - Add linkport group and function information for bf60x. - Separate uart and ctsrts pins into 2 groups. - Separate APAPI and alternative ATAPI pins into 2 groups. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
608a26a7 |
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27-Aug-2013 |
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> |
pinctrl: Add s5pv210 support to pinctrl-exynos This patch implements pinctrl support and adds device tree bindings for s5pv210. Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
63ca8db7 |
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22-Aug-2013 |
Axel Lin <axel.lin@ingics.com> |
pinctrl: palmas: PINCTRL_PALMAS needs to select PINMUX Fix below build error if !PINMUX. CC drivers/pinctrl/pinctrl-palmas.o drivers/pinctrl/pinctrl-palmas.c:741:21: error: variable 'palmas_pinmux_ops' has initializer but incomplete type drivers/pinctrl/pinctrl-palmas.c:742:2: error: unknown field 'get_functions_count' specified in initializer drivers/pinctrl/pinctrl-palmas.c:742:2: warning: excess elements in struct initializer [enabled by default] drivers/pinctrl/pinctrl-palmas.c:742:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default] drivers/pinctrl/pinctrl-palmas.c:743:2: error: unknown field 'get_function_name' specified in initializer drivers/pinctrl/pinctrl-palmas.c:743:2: warning: excess elements in struct initializer [enabled by default] drivers/pinctrl/pinctrl-palmas.c:743:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default] drivers/pinctrl/pinctrl-palmas.c:744:2: error: unknown field 'get_function_groups' specified in initializer drivers/pinctrl/pinctrl-palmas.c:744:2: warning: excess elements in struct initializer [enabled by default] drivers/pinctrl/pinctrl-palmas.c:744:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default] drivers/pinctrl/pinctrl-palmas.c:745:2: error: unknown field 'enable' specified in initializer drivers/pinctrl/pinctrl-palmas.c:745:2: warning: excess elements in struct initializer [enabled by default] drivers/pinctrl/pinctrl-palmas.c:745:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default] make[2]: *** [drivers/pinctrl/pinctrl-palmas.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
736658c5 |
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19-Aug-2013 |
Mark Brown <broonie@linaro.org> |
pinctrl: palmas: Fix device name in Kconfig text The device family is called Palmas so there should be a 's' on the end of the name. Signed-off-by: Mark Brown <broonie@linaro.org> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0a8d3e24 |
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06-Aug-2013 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: palmas: add pincontrol driver TI Palmas series Power Management IC have multiple pins which can be configured for different functionality. This pins can be configured for different function. Also their properties like pull up/down, open drain enable/disable are configurable. Add support for pincontrol driver Palmas series device like TPS65913, TPS80036. The driver supports to be register from DT only. Changes from V1: - Add generic property for pins and functions in pinconf-generic. - Add APIs to map the DT and subnode. - Move common utils APIs to the pinctrl-utils from this file. - Update the binding document accordingly. Changes from V2: - Add ack by Lee. - Correct the binding docs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ec243320 |
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10-Jul-2013 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl-baytrail: fix indentations There are two minor issues with indentation in the code. This patch fixes them. No functional changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
701016c0 |
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20-Jun-2013 |
Srinivas KANDAGATLA <srinivas.kandagatla@st.com> |
pinctrl: st: Add pinctrl and pinconf support. This patch add pinctrl support to ST SoCs. About hardware: ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle pin configurations. Each multi-function pin is controlled, driven and routed through the PIO multiplexing block. Each pin supports GPIO functionality (ALT0) and multiple alternate functions(ALT1 - ALTx) that directly connect the pin to different hardware blocks. When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO block. Otherwise the PIO multiplexing block configures these parameters and retiming the signal. About driver: This pinctrl driver manages both PIO and PIO-mux block using pinctrl, pinconf, pinmux, gpio subsystems. All the pinctrl related config information can only come from device trees. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
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#
b58f0273 |
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20-Jun-2013 |
James Hogan <jhogan@kernel.org> |
pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver Add a pin control driver for the TZ1090's low power pins via the powerdown controller SOC_GPIO_CONTROL registers. These pins have individually controlled pull-up, and group controlled schmitt, slew-rate, drive-strength, and power-on-start (pos). The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the ir_mod_stable_out and ir_mod_power_out functions respectively. If no function is set they remain in GPIO mode. These muxes can be overridden by requesting them as GPIOs. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-doc@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d5025f9f |
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20-Jun-2013 |
James Hogan <jhogan@kernel.org> |
pinctrl-tz1090: add TZ1090 pinctrl driver Add a pin control driver for the main pins on the TZ1090 SoC. This doesn't include the low-power pins as they're controlled separately via the Powerdown Controller (PDC) registers. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-doc@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
83978253 |
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10-Jun-2013 |
Doug Anderson <dianders@chromium.org> |
ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be missing the pincontrol definitions. Move PINCTRL selects to the arch level since we should be enabling the code for all exynos variants. Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS kernel config. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
a5d811bb |
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18-Jun-2013 |
Mathias Nyman <mathias.nyman@linux.intel.com> |
pinctrl: add Intel BayTrail GPIO/pinctrl support Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins. Supports gpio interrupts and ACPI gpio events Pins may be muxed to alternate function instead of gpio by firmware. This driver does not touch the pin muxing and expect firmare to set pin muxing and pullup/down properties properly. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d3e51161 |
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10-Jun-2013 |
Heiko Stübner <heiko@sntech.de> |
pinctrl: add pinctrl driver for Rockchip SoCs This driver adds support the Cortex-A9 based SoCs from Rockchip, so at least the RK2928, RK3066 (a and b) and RK3188. Earlier Rockchip SoCs seem to use similar mechanics for gpio handling so should be supportable with relative small changes. Pull handling on the rk3188 is currently a stub, due to it being a bit different to the earlier SoCs. Pinmuxing as well as gpio (and interrupt-) handling tested on a rk3066a based machine. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
78bafc66 |
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28-May-2013 |
Jingchang Lu <b35083@freescale.com> |
pinctrl: add VF610 pinctrl driver Adds Freescale Vybrid VF610 pin controller driver to IMX common pinctrl driver framework. Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
af99a750 |
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20-May-2013 |
Heiko Stuebner <heiko@sntech.de> |
pinctrl: Add pinctrl-s3c24xx driver The s3c24xx pins follow a similar pattern as the other Samsung SoCs and can therefore reuse the already introduced infrastructure. The s3c24xx SoCs have one design oddity in that the first 4 external interrupts do not reside in the eint pending register but in the main interrupt controller instead. We solve this by forwarding the external interrupt from the main controller into the irq domain of the pin bank. The masking/acking of these interrupts is handled in the same way. Furthermore the S3C2412/2413 SoCs contain another oddity in that they keep the same 4 eints in the main interrupt controller and eintpend register and requiring ack operations to happen in both. This is solved by using different compatible properties for the wakeup eint node which set a property accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
21e59123 |
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21-Mar-2013 |
Shawn Guo <shawn.guo@linaro.org> |
pinctrl: add pinctrl driver for imx6sl Add a pinctrl driver for i.MX6 SoloLite based on pinctrl-imx core driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
3f551d6a |
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21-Mar-2013 |
Shawn Guo <shawn.guo@linaro.org> |
pinctrl: add pinctrl driver for imx6dl The imx6dl is a derivative of imx6q with very limited difference. These two SoCs are so compatible that they can be handled as one platform in software. That said, we will not have target SOC_IMX6DL but just reusing SOC_IMX6Q. That's why the pinctrl-imx6dl driver is added here with symbol PINCTRL_IMX6Q controlling the build of it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
61dd7261 |
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18-Mar-2013 |
Tomasz Figa <tomasz.figa@gmail.com> |
pinctrl: Add pinctrl-s3c64xx driver This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
170c6152 |
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19-Feb-2013 |
Tony Prisk <linux@prisktech.co.nz> |
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500 This patch adds support for the GPIO/pinmux controller found on the VIA VT8500 and Wondermedia WM8xxx-series SoCs. Each pin within the controller is capable of operating as a GPIO or as an alternate function. The pins are numbered according to their control bank/bit so that if new pins are added, the existing numbering is maintained. All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and WM8850. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
62194200 |
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13-Mar-2013 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
pinctrl: remove pxa pinctrl driver pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single could support DT mode & pin configuration. Use pinctrl-single driver to support MMP/PXA silicons instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9dddb4df |
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17-Feb-2013 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
pinctrl: single: support generic pinconf Support the operation of generic pinconf. The supported config arguments are INPUT_SCHMITT, INPUT_SCHMITT_ENABLE, DRIVE_STRENGHT, BIAS_DISABLE, BIAS_PULLUP, BIAS_PULLDOWN, SLEW_RATE. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a1ed2670 |
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18-Jan-2013 |
Kukjin Kim <kgene.kim@samsung.com> |
pinctrl: exynos: change PINCTRL_EXYNOS option Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a8f96e41 |
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28-Jan-2013 |
Patrice Chotard <patrice.chotard@stericsson.com> |
pinctrl/abx500: add AB8540 sub-driver Add AB8540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
09dbec3f |
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28-Jan-2013 |
Patrice Chotard <patrice.chotard@stericsson.com> |
pinctrl/abx500: add AB9540 sub-driver Add AB9540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1aa2d8d4 |
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28-Jan-2013 |
Patrice Chotard <patrice.chotard@stericsson.com> |
pinctrl/abx500: add AB8505 sub-driver Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3c937993 |
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08-Jan-2013 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl/abx500: add AB8500 sub-driver This adds a subdriver for the AB8500 pinctrl portions. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0493e649 |
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08-Jan-2013 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: add abx500 pinctrl driver core This adds the AB8500 core driver, which will be utilized by the follow-on drivers for different ABx500 variants. Sselect the driver from the DBX500_SOC, as this chip is powering and clocking that SoC. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6e54d8d2 |
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15-Dec-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/ Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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#
0e37f88d |
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18-Jan-2013 |
Maxime Ripard <mripard@kernel.org> |
ARM: sunxi: Add pinctrl driver for Allwinner SoCs The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
7452b64d |
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18-Jan-2013 |
Kukjin Kim <kgene.kim@samsung.com> |
pinctrl: exynos: change PINCTRL_EXYNOS option Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b6ae7a26 |
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08-Jan-2013 |
Pritesh Raithatha <praithatha@nvidia.com> |
pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoC This adds a driver for the Tegra114 pinmux, and required parameterization data for Tegra114. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra114-pinmux". Originally written by Pritesh. ldewangan: - cleanup the patches, - remove non-require tables. - Use module_platform_driver() for driver registartion. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f9925b5f |
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27-Dec-2012 |
Kukjin Kim <kgene.kim@samsung.com> |
pinctrl: samsung: removing duplicated condition for PINCTRL_SAMSUNG Now, PINCTRL_SAMSUNG should be enabled with PINCTRL_EXYNOS so we don't need to add 'depends on' condition already added in PINCTRL_EXYNOS. Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d279bc77 |
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27-Nov-2012 |
Axel Lin <axel.lin@ingics.com> |
pinctrl: Drop selecting PINCONF for MMP2, PXA168 and PXA910 These drivers do not need to select PINCONF. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f0b9a7e5 |
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09-Oct-2012 |
Thomas Abraham <thomas.abraham@linaro.org> |
pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller module in EXYNOS5440 is different from the pin controller found on other Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is independent of the Samsung pinctrl framework. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
cbc351ab |
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15-Nov-2012 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl/samsung: don't allow enabling pinctrl-samsung standalone The main samsung pinctrl module references the specific exynos4210 pinctrl driver, which selects the main driver in Kconfig. Making the main driver a silent "bool" option avoid this potential build error if CONFIG_PINCTRL_SAMSUNG=y && CONFIG_PINCTRL_EXYNOS4=n: drivers/built-in.o:(.rodata+0x4e4): undefined reference to `exynos4210_pin_ctrl' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
507ccdbf |
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11-Nov-2012 |
Axel Lin <axel.lin@ingics.com> |
pinctrl: tegra: Make PINCTRL_TEGRA select PINMUX && PINCONF Then we can remove "select PINMUX && PINCONF" from PINCTRL_TEGRA{20,30}. This simplifies the dependency. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
90db8a14 |
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11-Nov-2012 |
Axel Lin <axel.lin@ingics.com> |
pinctrl: mxs: Make PINCTRL_MXS select PINMUX && PINCONF Then we can remove "select PINMUX && PINCONF" from PINCTRL_IMX{23,28}. This simplifies the dependency. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d3e26f2f |
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27-Sep-2012 |
Barry Song <Baohua.Song@csr.com> |
pinctrl: sirf: enable the driver support new SiRFmarco SoC The driver supports old up SiRFprimaII SoCs, this patch makes it support the new SiRFmarco as well. SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to disable GPIO pad, we should write 1 to the corresponding bit in the new CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
06763c74 |
|
24-Oct-2012 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pinctrl: mvebu: move to its own directory Like the spear platform, the mvebu platform has multiple files: one core file, and then one file per SoC family. More files will be added later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to pinctrl-mvebu. For those reasons, having a separate subdirectory, drivers/pinctrl/mvebu/ makes sense, and it had already been suggested by Linus Wallej when the driver was originally submitted. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
55d2e40d |
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24-Oct-2012 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pinctrl: mvebu: allow plat-orion architectures to use pinctrl-mvebu The mach-kirkwood and mach-dove architectures have not yet been integrated into the mach-mvebu directory, which should ultimately contain the support for all Marvell SoCs from the Engineering Business Unit. However, before this can happen, we need to let mach-kirkwood and mach-dove use the pinctrl-mvebu driver, which supports the kirkwood and dove SoC families. In order to do that, we make this driver available as soon as PLAT_ORION is selected, instead of using ARCH_MVEBU as a condition. In the long term, PLAT_ORION should disappear and be fully replaced by ARCH_MVEBU, but the plan is to make the migration step by step, by first having the existing mach-* directories for Marvell SoCs converge on several infrastructures, including the pinctrl one. Also, like the spear pinctrl driver, we put all pinctrl-mvebu Kconfig options under a if, in order to avoid having certain options (PINCTRL_DOVE, PINCTRL_KIRKWOOD, etc.) selecting an option (PINCTLR_MVEBU) which itself has a dependency (on ARCH_MVEBU). In this a construct, the dependency is in fact ignored due to the selects. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
924da314 |
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06-Nov-2012 |
Axel Lin <axel.lin@ingics.com> |
pinctrl: samsung and exynos need to depend on OF && GPIOLIB This patch fixes below build error when !CONFIG_OF_GPIO. CC drivers/pinctrl/pinctrl-samsung.o drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_pinctrl_parse_dt_pins': drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' [-Wunused-variable] drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register': drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no member named 'of_node' make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 The samsung pinctrl driver supports only device tree enabled platforms. Thus make PINCTRL_SAMSUNG depend on OF && GPIOLIB. The reason to depend on GPIOLIB is CONFIG_OF_GPIO only available when GPIOLIB is selected. Since PINCTRL_EXYNOS4 select PINCTRL_SAMSUNG, thus also make PINCTRL_EXYNOS4 depend on OF && GPIOLIB. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6732ae5c |
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12-Jul-2012 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
ARM: at91: add pinctrl support This is also include the gpio controller as the IP share both. Each soc will have to describe the SoC limitation and pin configuration via DT. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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#
e1b2dc70 |
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27-Sep-2012 |
Simon Arlott <simon@octiron.net> |
pinctrl: add bcm2835 driver The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt controller, and pinmux/control device. Original driver by Simon Arlott. Rewrite including GPIO chip device by Chris Boot. Upstreaming changes by Stephen Warren: * Wrote DT binding documentation. * Changed brcm,function to an integer to more directly match the datasheet, and to match brcm,pins being an integer. * Implemented pull-up/down pin config. * Removed read-only DT property and related code. The restriction this implemented are driven by the board, not the GPIO HW block, so don't really make sense of a HW block binding, were in general incomplete (since they could only know about the few pins hard-coded into the Raspberry Pi B board design and not the uncommitted GPIOS), and are better represented simply by not writing incorrect data into pin configuration nodes. * Don't set GPIO_IN function select in gpio_request_enable() to avoid glitches; defer this to gpio_set_direction(). Consequently, removed empty bcm2835_pmx_gpio_request_enable(). * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank. * Lifted use of enabled_irq_map[] outside the per-interrupt loop in IRQ handler, thus fixing an issue where the code was indexing into enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID. * Removed locking in IRQ handler, since all other code uses spin_lock_irqsave() and so guarantees it doesn't run concurrently with the handler. * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of bcm2835_gpio_pins[]. * Remove range-checking from bcm2835_pctl_get_groups_count() since we've decided to trust the pinctrl core. * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set() directly for simplicity. * Fixed body of dt_free_map() to match latest dt_node_to_map(). * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl core owns doing this. * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more descriptive. * Simplified remove(); removed call to non-existent pinctrl_remove_gpio_range(), remove early return on error. * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's base GPIO number. * Error-handling cleanups in probe(). * Switched to module_platform_driver() rather than open-coding. * Made pin, group, and function names lower-case. * s/broadcom/brcm/ in DT property names. * s/2708/2835/. * Fixed a couple minor checkpatch warnings, and other minor cleanup. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Chris Boot <bootc@bootc.net> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
463e270f |
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13-Sep-2012 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pinctrl: mvebu: add pinctrl driver for Armada XP This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
5f597bb2 |
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13-Sep-2012 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pinctrl: mvebu: add pinctrl driver for Armada 370 This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
9d4b1632 |
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13-Sep-2012 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
pinctrl: mvebu: kirkwood pinctrl driver This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
c9f95ced |
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13-Sep-2012 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
pinctrl: mvebu: dove pinctrl driver This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
7e8d9415 |
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13-Sep-2012 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
pinctrl: mvebu: pinctrl driver core This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
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#
e316cb2b |
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19-May-2012 |
John Crispin <blogic@openwrt.org> |
OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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#
3f8c50c9 |
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27-Aug-2012 |
John Crispin <blogic@openwrt.org> |
OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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#
43b169db |
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06-Sep-2012 |
Thomas Abraham <thomas.abraham@linaro.org> |
pinctrl: add exynos4210 specific extensions for samsung pinctrl driver Add information about the Exynos4210 pin banks and driver data which is used by the Samsung pinctrl driver. In addition to this, the support for external gpio and wakeup interrupt support is included and hooked up with the Samsung pinctrl driver. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
30574f0d |
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06-Sep-2012 |
Thomas Abraham <thomas.abraham@linaro.org> |
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
b9aa8f13 |
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09-Aug-2012 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: pinctrl-imx: add imx35 pinctrl driver This is mostly cut'n'paste from the imx51 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx35.h. Changes since (implicit) v1 - remove references to file names in binding documentation - remove sed commands from comments in driver - add explicit numbers for pins and functions Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f79c5ed9 |
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09-Aug-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl/nomadik: add STn8815 ASIC support This adds support for the STN8815 ASIC for the Nomadik pin controller. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
45a1b531 |
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20-Jul-2012 |
Patrice Chotard <patrice.chotard@stericsson.com> |
pinctrl/nomadik: add ASIC DB8450 pinctrl driver This implements a subdriver for the DB8540 ASIC for the Nomadik pin controller. Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8b8b091b |
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10-Jul-2012 |
Tony Lindgren <tony@atomide.com> |
pinctrl: Add one-register-per-pin type device tree based pinctrl driver Add one-register-per-pin type device tree based pinctrl driver. This driver has been tested on omap2+ series of processors, where there is either an 8 or 16-bit padconf register for each pin. Support for other similar pinmux controllers can be added. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3c94d1bb |
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18-Jun-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: select the proper symbol The Kconfig entry for the COH901 pin controller depended on PINMUX_U300 which is stale, use PINCTRL_U300 as it is called these days. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4f6a16bf |
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15-May-2012 |
Dong Aisheng <dong.aisheng@linaro.org> |
pinctrl: pinctrl-imx: add imx51 pinctrl driver ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
93fbd3c0 |
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15-May-2012 |
Dong Aisheng <dong.aisheng@linaro.org> |
pinctrl: pinctrl-imx: add imx53 pinctrl driver ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0fa7be40 |
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15-May-2012 |
Arnd Bergmann <arnd@arndb.de> |
ARM: nomadik: enable PINCTRL_NOMADIK where needed The nomadik gpio code has been converted to pinctrl, but the nomadik platform still expects the old code to be present. Change it to use the new one instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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#
d41af627 |
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03-May-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl/nomadik: implement pin configuration This implements the pin configuration interface for the Nomadik pin controller. As part of the exercise we add a bit in the pin_cfg_t for the Nomadik pinctrl driver that indicates if the pin should be forced into GPIO mode. This is not done to go behind the back of the GPIO subsystem, but to ensure that default modes can be set by hogs on boot and system suspend/resume states. It was used implicitly by the old code defining all config settings and modes in a single config word but we now have a split between pinmux and pinconf leading to the need to have this. We also add a bit for explicitly setting sleepmode of the pin. This was previously handled by custom calls with the _sleep() suffix, but we now have one single interface into the configuration so we replace this with a bit indicating that the pin shall be configured into sleep mode. Some of the configuration can be refactored later to use less custom fields on the pin_cfg_t but we are currently leaving the old function calls in place so we stay compatible. ChangeLog v1->v2: - Drop a hunk changing pinmuxing for GPIO and move it over to the preceding pinmux patch. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dbfe8ca2 |
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02-May-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl/nomadik: implement pin multiplexing Implements basic pinmux for the Nomadik pin controller. The plan is to split the existing singular pin config interface nmk_config_pin(), nmk_config_pins(), that will configure muxing and other settings at the same time, into two interfaces by splitting the code in pinmux and pinctrl and eventually deleting the old interface and its helper functions when all users are gone. nmk_gpio_set_mode() and nmk_gpio_get_mode() are two older interfaces for just configuring muxing/altfunctions that will also be replaced in the end. We take some extra care to handle the glitch-avoidance here, but it is simpler now since there is only one altsetting per pingroup so we know immediately if we need to avoid altfunc C glitches for a certain group. As part of the makeover implement the .request() and .free() calls on the GPIO chips and have them call back into the pinctrl layer to reserve GPIOs. ChangeLog v1->v2: - Rebased on pinctrl-mergebase-20120418 so we get the latest driver infrastructure where function count is done by a fixed value and we can drop a few range checks since this is now handled by the core. - Include a GPIO muxing hunk erroneously part of the pin config patch. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e98ea774 |
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26-Apr-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl/nomadik: basic Nomadik pinctrl interface This adds a scratch pin control interface to the Nomadik pinctrl driver, and defines the pins and groups in the DB8500 ASIC. We define GPIO ranges to cover the pins exposed. The DB8500 has more pins than this but we restrict the driver to the pins that can be controlled from the combined GPIO and pin control hardware to begin with. ChangeLog v1->v2: - Base on the latest pinctrl development from pinctrl-mergebase-20120418 so we can get rid of legacy group count mechanism. Also drop the range checks for group index, this is handled by the core now. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
17723111 |
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27-Apr-2012 |
Shawn Guo <shawn.guo@linaro.org> |
pinctrl: add pinctrl-mxs support Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d8fe3572 |
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27-Apr-2012 |
Dong Aisheng <dong.aisheng@linaro.org> |
pinctrl: pinctrl-imx: add imx6q pinctrl driver Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ae75ff81 |
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27-Apr-2012 |
Dong Aisheng <dong.aisheng@linaro.org> |
pinctrl: pinctrl-imx: add imx pinctrl core driver The driver has mux and config support while the gpio is still not supported. For select input setting, the driver will handle it internally and do not need user to take care of it. The pinctrl-imx core driver will parse the dts file and dynamically create the pinmux functions and groups. Each IMX SoC pinctrl driver should register pins with a pin register map including mux register and config register and select input map to core for proper operations. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
deda8287 |
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28-Mar-2012 |
Viresh Kumar <vireshk@kernel.org> |
pinctrl: Add SPEAr pinctrl drivers This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file for SPEAr pinctrl drivers. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
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#
630e2d04 |
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12-Apr-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: mark non-EXPERIMENTAL With the finalization of the external driver API and the device tree support, this subsystem is now mature and can be promoted to non-experimental status. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dc0b1aa3 |
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16-Nov-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: support pinconfig on the U300 This adds pin configuration support for the U300 driver pair, we can now read out the biasing and drive mode in debugfs and configure it using the new configuration API. ChangeLog v1->v2: - Migrate to pin config and generic pin config changes. ChangeLog v2->v3: - Adjust to generic pin config changes in v7 patch set. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
394349f7 |
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24-Nov-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: introduce generic pin config This is a split-off from the earlier patch set which adds generic pin configuration for the pin controllers that want it. Since we may have a system with mixed generic and custom pin controllers, we pass a boolean in the pin controller ops vtable to indicate if it is generic. ChangeLog v1->v5: - Follow parent patch versioning number system. - Document the semantic meaning of return values from pin config get functions, so we can iterate over pins and check their properties from debugfs as part of the generic config code. - Use proper cast functions in the generic debugfs pin config file. - Expand generic config to optionally cover groups too. ChangeLog v5->v6: - Update to match underlying changes. ChangeLog v6->v7: - Drop DRIVE_OFF parameter, use bias high impedance for this - Delete argument for drive modes push-pull, od and os. These are now just state transitions. - Delete slew rate rising/falling due to discussions on on proper semantics - Drop config wakeup, struct irq_chip does this for now, add back if need be. - Set PIN_CONFIG_END to 0x7fff making room for custom config parameters from 0x8000 and up. - Prefix accessor functions with pinconf_
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#
971dac71 |
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01-Feb-2012 |
Stephen Warren <swarren@nvidia.com> |
pinctrl: add a driver for NVIDIA Tegra This adds a driver for the Tegra pinmux, and required parameterization data for Tegra20 and Tegra30. The driver is initially added with driver name and device tree compatible value that won't cause this driver to be used. A later change will switch the pinctrl driver to use the correct values, switch the old pinmux driver to be disabled, and update all code that uses the old pinmux APIs to use the new pinctrl APIs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net> [squashed "fix case of Tegra30's foo_groups[] arrays"] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f4e66983 |
|
03-Jan-2012 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
pinctrl: enable pinmux for mmp series Support PXA168/PXA910/MMP2 pinmux. Now only support function switch. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> [Rebase and fix some whitespace issues] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3bece55a |
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18-Dec-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: rename U300 and SIRF pin controllers For stringent order, rename the pinmux-* pin controllers to pinctrl-* and also rename the Kconfig symbols and in-kernel users. Cc: Rongjun Ying <Rongjun.Ying@csr.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ae6b4d85 |
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19-Oct-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: add a pin config interface This add per-pin and per-group pin config interfaces for biasing, driving and other such electronic properties. The details of passed configurations are passed in an opaque unsigned long which may be dereferences to integer types, structs or lists on either side of the configuration interface. ChangeLog v1->v2: - Clear split of terminology: we now have pin controllers, and those may support two interfaces using vtables: pin multiplexing and pin configuration. - Break out pin configuration to its own C file, controllers may implement only config without mux, and vice versa, so keep each sub-functionality of pin controllers separate. Introduce CONFIG_PINCONF in Kconfig. - Implement some core logic around pin configuration in the pinconf.c file. - Remove UNKNOWN config states, these were just surplus baggage. - Remove FLOAT config state - HIGH_IMPEDANCE should be enough for everyone. - PIN_CONFIG_POWER_SOURCE added to handle switching the power supply for the pin logic between different sources - Explicit DISABLE config enums to turn schmitt-trigger, wakeup etc OFF. - Update documentation to reflect all the recent reasoning. ChangeLog v2->v3: - Twist API around to pass around arrays of config tuples instead of (param, value) pairs everywhere. - Explicit drive strength semantics for push/pull and similar drive modes, this shall be the number of drive stages vs nominal load impedance, which should match the actual electronics used in push/pull CMOS or TTY totempoles. - Drop load capacitance configuration - I probably don't know what I'm doing here so leave it out. - Drop PIN_CONFIG_INPUT_SCHMITT_OFF, instead the argument zero to PIN_CONFIG_INPUT_SCHMITT turns schmitt trigger off. - Drop PIN_CONFIG_NORMAL_POWER_MODE and have a well defined argument to PIN_CONFIG_LOW_POWER_MODE to get out of it instead. - Drop PIN_CONFIG_WAKEUP_ENABLE/DISABLE and just use PIN_CONFIG_WAKEUP with defined value zero to turn wakeup off. - Add PIN_CONFIG_INPUT_DEBOUNCE for configuring debounce time on input lines. - Fix a bug when we tried to configure pins for pin controllers without pinconf support. - Initialized debugfs properly so it works. - Initialize the mutex properly and lock around config tampering sections. - Check the return value from get_initial_config() properly. ChangeLog v3->v4: - Export the pin_config_get(), pin_config_set() and pin_config_group() functions. - Drop the entire concept of just getting initial config and keeping track of pin states internally, instead ask the pins what state they are in. Previous idea was plain wrong, if the device cannot keep track of its state, the driver should do it. - Drop the generic configuration layout, it seems this impose too much restriction on some pin controllers, so let them do things the way they want and split off support for generic config as an optional add-on. ChangeLog v4->v5: - Introduce two symmetric driver calls for group configuration, .pin_config_group_[get|set] and corresponding external calls. - Remove generic semantic meanings of return values from config calls, these belong in the generic config patch. Just pass the return value through instead. - Add a debugfs entry "pinconf-groups" to read status from group configuration only, also slam in a per-group debug callback in the pinconf_ops so custom drivers can display something meaningful for their pins. - Fix some dangling newline. - Drop dangling #else clause. - Update documentation to match the above. ChangeLog v5->v6: - Change to using a pin name as parameter for the [get|set]_config() functions, as suggested by Stephen Warren. This is more natural as names will be what a developer has access to in written documentation etc. ChangeLog v6->v7: - Refactor out by-pin and by-name get/set functions, only expose the by-name functions externally, expose the by-pin functions internally. - Show supported pin control functionality in the debugfs pinctrl-devices file. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b4e3ac74 |
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16-Nov-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl/coh901: driver to request its pins This makes the COH 901 driver request muxing of its GPIO pins from the pinmux-u300 driver using the standard API calls. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ca402d37 |
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16-Nov-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: move the U300 GPIO driver to pinctrl This driver will be converted to a dual GPIO + pinctrl driver since it supports biasing and driving control options. Hopefully it can serve as an example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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45f034ef |
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05-Nov-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: hide subsystem from the populace Machines that have embedded pin controllers need to select them explicitly, so why broadcast their config options to menuconfig. We provide a helpful submenu for those machines that do select it, making it possible to enable debugging for example. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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393daa81 |
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09-Oct-2011 |
Rongjun Ying <Rongjun.Ying@csr.com> |
pinctrl: add a driver for the CSR SiRFprimaII pinmux This creates a pin controller driver for the SiRFprinaII pin mux portions. Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> [Fixup for changed function names and semantics in the v10 patch] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
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98da3529 |
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02-May-2011 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: add a driver for the U300 pinmux This adds a driver for the U300 pinmux portions of the system controller "SYSCON". It also serves as an example of how to use the pinmux subsystem. This driver also houses the platform data for the only supported platform. This deletes the old U300 driver in arch/arm/mach-u300 and replace it with a driver using the new subsystem. The new driver is considerably fatter than the old one, but it also registers all 467 pins of the system and adds the power and EMIF pin groups and corresponding functions. The idea is to use this driver as a a reference for other implementation so it needs to be as complete and verbose as possible. Reviewed-by: Barry Song <21cnbao@gmail.com> [Fixup for changed function names and semantics in the v10 patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2744e8af |
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02-May-2011 |
Linus Walleij <linus.walleij@linaro.org> |
drivers: create a pin control subsystem This creates a subsystem for handling of pin control devices. These are devices that control different aspects of package pins. Currently it handles pinmuxing, i.e. assigning electronic functions to groups of pins on primarily PGA and BGA type of chip packages which are common in embedded systems. The plan is to also handle other I/O pin control aspects such as biasing, driving, input properties such as schmitt-triggering, load capacitance etc within this subsystem, to remove a lot of ARM arch code as well as feature-creepy GPIO drivers which are implementing the same thing over and over again. This is being done to depopulate the arch/arm/* directory of such custom drivers and try to abstract the infrastructure they all need. See the Documentation/pinctrl.txt file that is part of this patch for more details. ChangeLog v1->v2: - Various minor fixes from Joe's and Stephens review comments - Added a pinmux_config() that can invoke custom configuration with arbitrary data passed in or out to/from the pinmux driver ChangeLog v2->v3: - Renamed subsystem folder to "pinctrl" since we will likely want to keep other pin control such as biasing in this subsystem too, so let us keep to something generic even though we're mainly doing pinmux now. - As a consequence, register pins as an abstract entity separate from the pinmux. The muxing functions will claim pins out of the pin pool and make sure they do not collide. Pins can now be named by the pinctrl core. - Converted the pin lookup from a static array into a radix tree, I agreed with Grant Likely to try to avoid any static allocation (which is crap for device tree stuff) so I just rewrote this to be dynamic, just like irq number descriptors. The platform-wide definition of number of pins goes away - this is now just the sum total of the pins registered to the subsystem. - Make sure mappings with only a function name and no device works properly. ChangeLog v3->v4: - Define a number space per controller instead of globally, Stephen and Grant requested the same thing so now maps need to define target controller, and the radix tree of pin descriptors is a property on each pin controller device. - Add a compulsory pinctrl device entry to the pinctrl mapping table. This must match the pinctrl device, like "pinctrl.0" - Split the file core.c in two: core.c and pinmux.c where the latter carry all pinmux stuff, the core is for generic pin control, and use local headers to access functionality between files. It is now possible to implement a "blank" pin controller without pinmux capabilities. This split will make new additions like pindrive.c, pinbias.c etc possible for combined drivers and chunks of functionality which is a GoodThing(TM). - Rewrite the interaction with the GPIO subsystem - the pin controller descriptor now handles this by defining an offset into the GPIO numberspace for its handled pin range. This is used to look up the apropriate pin controller for a GPIO pin. Then that specific GPIO range is matched 1-1 for the target controller instance. - Fixed a number of review comments from Joe Perches. - Broke out a header file pinctrl.h for the core pin handling stuff that will be reused by other stuff than pinmux. - Fixed some erroneous EXPORT() stuff. - Remove mispatched U300 Kconfig and Makefile entries - Fixed a number of review comments from Stephen Warren, not all of them - still WIP. But I think the new mapping that will specify which function goes to which pin mux controller address 50% of your concerns (else beat me up). ChangeLog v4->v5: - Defined a "position" for each function, so the pin controller now tracks a function in a certain position, and the pinmux maps define what position you want the function in. (Feedback from Stephen Warren and Sascha Hauer). - Since we now need to request a combined function+position from the machine mapping table that connect mux settings to drivers, it was extended with a position field and a name field. The name field is now used if you e.g. need to switch between two mux map settings at runtime. - Switched from a class device to using struct bus_type for this subsystem. Verified sysfs functionality: seems to work fine. (Feedback from Arnd Bergmann and Greg Kroah-Hartman) - Define a per pincontroller list of GPIO ranges from the GPIO pin space that can be handled by the pin controller. These can be added one by one at runtime. (Feedback from Barry Song) - Expanded documentation of regulator_[get|enable|disable|put] semantics. - Fixed a number of review comments from Barry Song. (Thanks!) ChangeLog v5->v6: - Create an abstract pin group concept that can sort pins into named and enumerated groups no matter what the use of these groups may be, one possible usecase is a group of pins being muxed in or so. The intention is however to also use these groups for other pin control activities. - Make it compulsory for pinmux functions to associate with at least one group, so the abstract pin group concept is used to define the groups of pins affected by a pinmux function. The pinmux driver interface has been altered so as to enforce a function to list applicable groups per function. - Provide an optional .group entry in the pinmux machine map so the map can select beteween different available groups to be used with a certain function. - Consequent changes all over the place so that e.g. debugfs present reasonable information about the world. - Drop the per-pin mux (*config) function in the pinmux_ops struct - I was afraid that this would start to be used for things totally unrelated to muxing, we can introduce that to the generic struct pinctrl_ops if needed. I want to keep muxing orthogonal to other pin control subjects and not mix these things up. ChangeLog v6->v7: - Make it possible to have several map entries matching the same device, pin controller and function, but using a different group, and alter the semantics so that pinmux_get() will pick all matching map entries, and store the associated groups in a list. The list will then be iterated over at pinmux_enable()/pinmux_disable() and corresponding driver functions called for each defined group. Notice that you're only allowed to map multiple *groups* to the same { device, pin controller, function } triplet, attempts to map the same device to multiple pin controllers will for example fail. This is hopefully the crucial feature requested by Stephen Warren. - Add a pinmux hogging field to the pinmux mapping entries, and enable the pinmux core to hog pinmux map entries. This currently only works for pinmuxes without assigned devices as it looks now, but with device trees we can look up the corresponding struct device * entries when we register the pinmux driver, and have it hog each pinmux map in turn, for a simple approach to non-dynamic pin muxing. This addresses an issue from Grant Likely that the machine should take care of as much of the pinmux setup as possible, not the devices. By supplying a list of hogs, it can now instruct the core to take care of any static mappings. - Switch pinmux group retrieveal function to grab an array of strings representing the groups rather than an array of unsigned and rewrite accordingly. - Alter debugfs to show the grouplist handled by each pinmux. Also add a list of hogs. - Dynamically allocate a struct pinmux at pinmux_get() and free it at pinmux_put(), then add these to the global list of pinmuxes active as we go along. - Go over the list of pinmux maps at pinmux_get() time and repeatedly apply matches. - Retrieve applicable groups per function from the driver as a string array rather than a unsigned array, then lookup the enumerators. - Make the device to pinmux map a singleton - only allow the mapping table to be registered once and even tag the registration function with __init so it surely won't be abused. - Create a separate debugfs file to view the pinmux map at runtime. - Introduce a spin lock to the pin descriptor struct, lock it when modifying pin status entries. Reported by Stijn Devriendt. - Fix up the documentation after review from Stephen Warren. - Let the GPIO ranges give names as const char * instead of some fixed-length string. - add a function to unregister GPIO ranges to mirror the registration function. - Privatized the struct pinctrl_device and removed it from the <linux/pinctrl/pinctrl.h> API, the drivers do not need to know the members of this struct. It is now in the local header "core.h". - Rename the concept of "anonymous" mux maps to "system" muxes and add convenience macros and documentation. ChangeLog v7->v8: - Delete the leftover pinmux_config() function from the <linux/pinctrl/pinmux.h> header. - Fix a race condition found by Stijn Devriendt in pin_request() ChangeLog v8->v9: - Drop the bus_type and the sysfs attributes and all, we're not on the clear about how this should be used for e.g. userspace interfaces so let us save this for the future. - Use the right name in MAINTAINERS, PIN CONTROL rather than PINMUX - Don't kfree() the device state holder, let the .remove() callback handle this. - Fix up numerous kerneldoc headers to have one line for the function description and more verbose documentation below the parameters ChangeLog v9->v10: - pinctrl: EXPORT_SYMBOL needs export.h, folded in a patch from Steven Rothwell - fix pinctrl_register error handling, folded in a patch from Axel Lin - Various fixes to documentation text so that it's consistent. - Removed pointless comment from drivers/Kconfig - Removed dependency on SYSFS since we removed the bus in v9. - Renamed hopelessly abbreviated pctldev_* functions to the more verbose pinctrl_dev_* - Drop mutex properly when looking up GPIO ranges - Return NULL instead of ERR_PTR() errors on registration of pin controllers, using cast pointers is fragile. We can live without the detailed error codes for sure. Cc: Stijn Devriendt <highguy@gmail.com> Cc: Joe Perches <joe@perches.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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