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7559e757 |
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14-Jul-2023 |
Rob Herring <robh@kernel.org> |
phy: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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7f1abed4 |
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29-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Add dual-phy support for NX1 SoC NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate configuration values to both PHY registers. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-7-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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25bba42f |
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29-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1c1597c8 |
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29-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC Add basic support for UniPhier NX1 SoC. This includes a compatible string, SoC-dependent data, and a function that set to 2-lane mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-5-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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4a90bbb4 |
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06-Jun-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Fix updating phy parameters The current driver uses a value from register TEST_O as the original value for register TEST_I, though, the value is overwritten by "param", so there is a bug that the original value isn't no longer used. The value of TEST_O[7:0] should be masked with "mask", replaced with "param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value. Fixes: c6d9b1324159 ("phy: socionext: add PCIe PHY driver support") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1623037842-19363-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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6861781a |
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29-Jan-2020 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Add SoC-dependent phy-mode function support Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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04de8fa2 |
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29-Jan-2020 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: uniphier-pcie: Add legacy SoC support for Pro5 Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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40d76346 |
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29-Jan-2020 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: socionext: Use devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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c6d9b132 |
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05-Sep-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: socionext: add PCIe PHY driver support Add a driver for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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