#
eeda4945 |
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12-Dec-2023 |
Stanley Chang <stanley_chang@realtek.com> |
phy: realtek: usb: add new driver for the Realtek RTD SoC USB 2.0 PHY Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 2.0 PHY transceivers. Note: New driver,remove the port status notification on legacy USB PHY. Use the generic PHY to notify the usb device connect and disconnect. To avoid using these PHYs would require describing the very same PHY using both the generic "phy" property and the deprecated "usb-phy" property. Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20231213031203.4911-2-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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7a784bcd |
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05-Nov-2023 |
Johan Hovold <johan+linaro@kernel.org> |
Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY" This reverts commit 134e6d25f6bd06071e5aac0a7eefcea6f7713955. The recently added Realtek PHY drivers depend on the new port status notification mechanism which was built on the deprecated USB PHY implementation and devicetree binding. Specifically, using these PHYs would require describing the very same PHY using both the generic "phy" property and the deprecated "usb-phy" property which is clearly wrong. We should not be building new functionality on top of the legacy USB PHY implementation even if it is currently stuck in some kind of transitional limbo. Revert the new Realtek PHY drivers for now so that the port status notification interface can be reverted and replaced. Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY") Cc: stable@vger.kernel.org # 6.6 Cc: Stanley Chang <stanley_chang@realtek.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231106110654.31090-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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16d3a71c |
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29-Jun-2023 |
Minda Chen <minda.chen@starfivetech.com> |
phy: starfive: Add JH7110 USB 2.0 PHY driver Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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134e6d25 |
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24-Jul-2023 |
Stanley Chang <stanley_chang@realtek.com> |
phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 2.0 PHY transceivers. Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20230725033318.8361-2-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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99d9ccd9 |
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24-Jul-2022 |
Vincent Shih <vincent.sunplus@gmail.com> |
phy: usb: Add USB2.0 phy driver for Sunplus SP7021 Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by: Vincent Shih <vincent.sunplus@gmail.com> Link: https://lore.kernel.org/r/1658717052-26142-2-git-send-email-vincent.sunplus@gmail.com [vkoul: remove trailing line in driver file] Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
a4a86d27 |
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09-May-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
phy: phy-can-transceiver: Add support for generic CAN transceiver driver The driver adds support for generic CAN transceivers. Currently the modes supported by this driver are standby and normal modes for TI TCAN1042 and TCAN1043 CAN transceivers. The transceiver is modelled as a phy with pins controlled by gpios, to put the transceiver in various device functional modes. It also gets the phy attribute max_link_rate for the usage of CAN drivers. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20210510051006.11393-4-a-govindraju@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
2ff8a1ee |
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18-Feb-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
phy: Add Sparx5 ethernet serdes PHY driver Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
31de313d |
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16-Nov-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
PHY: Ingenic: Add USB PHY driver using generic PHY framework. Used the generic PHY framework API to create the PHY, this driver supoorts USB OTG PHY used in JZ4770 SoC, JZ4775 SoC, JZ4780 SoC, X1000 SoC, X1830 SoC and X2000 SoC. Co-developed-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com> Signed-off-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201116141906.11758-4-zhouyanjie@wanyeetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
1cce8f73 |
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27-Aug-2020 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
phy: Add USB3 PHY support for Intel LGM SoC Add support for USB PHY on Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
4a33bea0 |
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29-Jun-2020 |
Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> |
phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
133552bf |
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25-May-2020 |
Tiezhu Yang <yangtiezhu@loongson.cn> |
phy: Remove CONFIG_ARCH_* check for related subdir in Makefile If CONFIG_ARCH_ROCKCHIP is not set but COMPILE_TEST is set, the file in the subdir rockchip can not be built due to CONFIG_ARCH_ROCKCHIP check in drivers/phy/Makefile. Since the related configs in drivers/phy/rockchip/Kconfig depend on ARCH_ROCKCHIP, so remove CONFIG_ARCH_ROCKCHIP check for subdir rockchip in drivers/phy/Makefile. The other CONFIG_ARCH_* about allwinner, amlogic, mediatek, renesas and tegra have the same situation, so remove them too. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/1590412138-13903-2-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
92279423 |
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16-Dec-2019 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
phy: intel-lgm-emmc: Add support for eMMC PHY Add support for eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
4e99276a |
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27-Jul-2019 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
phy: enable compile-testing for the Lantiq PHY drivers Unconditionally include the lantiq subdirectory in the phy Makefile. All drivers in there have their dependencies maintained. One of these (optional) dependencies is COMPILE_TEST, however this can only be evaluated when Kconfig scans the lantiq subdirectory. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
dddc97e8 |
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07-Dec-2018 |
Maxime Ripard <mripard@kernel.org> |
phy: dphy: Add configuration helpers The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
efe81bea |
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15-Nov-2018 |
Li Jun <jun.li@nxp.com> |
phy: add driver for Freescale i.MX8MQ USB3 PHY This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
51f6b410 |
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04-Oct-2018 |
Quentin Schulz <quentin.schulz@bootlin.com> |
phy: add driver for Microsemi Ocelot SerDes muxing The Microsemi Ocelot can mux SerDes lanes (aka macros) to different switch ports or even make it act as a PCIe interface. This adds support for the muxing of the SerDes. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5ab43d0f |
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21-Aug-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
phy: socionext: add USB3 PHY driver for UniPhier SoC Add a driver for PHY interface built into USB3 controller implemented in UniPhier SoCs. This driver supports High-Speed PHY and Super-Speed PHY. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Motoya Tanigawa <tanigawa.motoya@socionext.com> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
c8b427ed |
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09-Aug-2018 |
Scott Telford <stelford@cadence.com> |
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
b2441318 |
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01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
dea54fba |
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19-Aug-2017 |
Hauke Mehrtens <hauke@hauke-m.de> |
phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module This driver starts the DWC2 core(s) built into the XWAY SoCs and provides the PHY interfaces for each core. The phy instances can be passed to the dwc2 driver, which already supports the generic phy interface. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Rob Herring <robh@kernel.org> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17127/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
2411a736 |
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17-Aug-2017 |
John Crispin <john@phrozen.org> |
phy: ralink-usb: add driver for Mediatek/Ralink Add a driver to setup the USB phy on Mediatek/Ralink SoCs. The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
cd4ec4b0 |
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03-Aug-2017 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
phy: phy-mt65xx-usb3: add mediatek directory and rename file The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
6d6ce40f |
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22-May-2017 |
Tony Lindgren <tony@atomide.com> |
phy: cpcap-usb: Add CPCAP PMIC USB support Some Motorola phones like droid 4 use a custom CPCAP PMIC that has a multiplexing USB PHY. This USB PHY can operate at least in four modes using pin multiplexing and two control GPIOS: - Pass through companion PHY for the SoC USB PHY - ULPI PHY for the SoC - Pass through USB for the modem - UART debug console for the SoC This patch adds support for droid 4 USB PHY and debug UART modes, support for other modes can be added later on as needed. Both peripheral and host mode are working for the USB. The host mode depends on the cpcap-charger driver for VBUS. VBUS and ID pin detection are done using cpcap-adc IIO ADC driver. Cc: devicetree@vger.kernel.org Cc: Marcel Partap <mpartap@gmx.net> Cc: Michael Scott <michael.scott@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
0b56e9a7 |
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10-May-2017 |
Vivek Gautam <vivek.gautam@codeaurora.org> |
phy: Group vendor specific phy drivers Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
e78f3d15 |
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05-Apr-2017 |
Vivek Gautam <vivek.gautam@codeaurora.org> |
phy: qcom-qmp: new qmp phy driver for qcom-chipsets Qualcomm SOCs have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Add a new driver, based on generic phy framework, for this phy controller. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
ca04d9d3 |
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05-Apr-2017 |
Vivek Gautam <vivek.gautam@codeaurora.org> |
phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips PHY transceiver driver for QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller present on Qualcomm chipsets. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
9200c6f1 |
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08-Feb-2017 |
Rafał Miłecki <rafal@milecki.pl> |
Revert "phy: Add USB3 PHY support for Broadcom NSP SoC" This reverts commit d7bc1a7d41bf ("phy: Add USB3 PHY support for Broadcom NSP SoC") as we already have driver for this PHY (shared by NS and NSP). It was added in commit e5666281d9ea ("phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar"). Instead of adding separated driver & duplicating code we should work on improving existing (old) one. Thanks to work done by Broadcom we know there is MDIO bus we weren't aware of & we know register names which makes initialization more clear. This is very valuable info and we should work on using it in existing driver afterwards. Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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#
cf0adb8e |
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13-Feb-2017 |
Jaehoon Chung <jh80.chung@samsung.com> |
phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Add support for Generic PHY framework about Exynos SoCs. Current Exynos PCIe driver doesn't use the PHY framework, which makes it difficult to upstream the other Exynos variants because of different PHY registers. Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe driver. [bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update copyright year, both per Vivek] Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
d7bc1a7d |
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17-Jan-2017 |
Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> |
phy: Add USB3 PHY support for Broadcom NSP SoC This patch adds support for Broadcom NSP USB3 PHY Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
e2427b09 |
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25-Jan-2017 |
Stephen Boyd <stephen.boyd@linaro.org> |
phy: Add support for Qualcomm's USB HS phy The high-speed phy on qcom SoCs is controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: <devicetree@vger.kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
605b8652 |
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25-Jan-2017 |
Stephen Boyd <stephen.boyd@linaro.org> |
phy: Add support for Qualcomm's USB HSIC phy The HSIC USB controller on qcom SoCs has an integrated all digital phy controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Rob Herring <robh@kernel.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
fb954c48 |
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15-Nov-2016 |
Peter Griffin <peter.griffin@linaro.org> |
phy: stih41x-usb: Remove usb phy driver and dt binding documentation. This phy is only used on STiH415/6 based silicon, and support for these SoC's is being removed from the kernel. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
4eb8eb1d |
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15-Nov-2016 |
Peter Griffin <peter.griffin@linaro.org> |
phy: phy-miphy365x: Remove miphy365 driver and dt binding documentation. This phy is only used on STiH415/6 based silicon, and support for these SoC's is being removed from the kernel. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
7965ba05 |
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01-Oct-2016 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
phy: meson: add USB2 PHY support for Meson8b and GXBB This is a new driver for the USB PHY found in Meson8b and GXBB SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
e96be45c |
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23-Aug-2016 |
Chris Zhong <zyw@rock-chips.com> |
phy: Add USB Type-C PHY driver for rk3399 Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB Type-C PHY is designed to support the USB3 and DP applications. The USB3 operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2 data rates. This driver create 2 PHY devices separately for USB3 and DisplyPort, and registers them under the child node. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Tested-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
fcffee3d |
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01-Sep-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
phy: add a driver for the Rockchip SoC internal PCIe PHY This patch to add a generic PHY driver for rockchip PCIe PHY. Access the PHY via registers provided by GRF (general register files) module. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
0e08d2a7 |
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22-Jul-2016 |
Frank Wang <frank.wang@rock-chips.com> |
phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy The newer SoCs (rk3366, rk3399) take a different usb-phy IP block than rk3288 and before, and most of phy-related registers are also different from the past, so a new phy driver is required necessarily. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Suggested-by: Heiko Stuebner <heiko@sntech.de> Suggested-by: Guenter Roeck <linux@roeck-us.net> Suggested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
e5666281 |
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11-Aug-2016 |
Rafał Miłecki <rafal@milecki.pl> |
phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar Northstar is a family of SoCs used in home routers. They have USB 2.0 and 3.0 controllers with PHYs that need to be properly initialized. This driver provides PHY init support in a generic way and can be bound with XHCI controller driver. There aren't any public datasheets from Broadcom so we can't have nice defines for all used bits. It means we just follow Broadcom's initialization procedure using their magic values. We were quite lucky actually that Broadcom put some comments in their SDK reference code explaining what given writes are responsible for. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
f2e60041 |
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09-May-2016 |
David Lechner <david@lechnology.com> |
phy: da8xx-usb: new driver for DA8xx SoC USB PHY This is a new phy driver for the SoC USB controllers on the TI DA8xx family of microcontrollers. The USB 1.1 PHY is just a simple on/off. The USB 2.0 PHY also allows overriding the VBUS and ID pins. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
4484f730 |
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09-Jun-2016 |
Pramod Kumar <pramod.kumar@broadcom.com> |
phy: Add Northstar2 PCI Phy support Add PCI Phy support for Broadcom Northstar2 SoCs. This driver uses the interface from the iproc mdio mux driver to enable the devices respective phys. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d3feb406 |
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14-Apr-2016 |
Rafał Miłecki <zajec5@gmail.com> |
phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar Northstar is a family of SoCs used in home routers. They have USB 2.0 and 3.0 controllers with PHYs that need to be properly initialized. This driver provides PHY init support in a generic way and can be bound with an EHCI controller driver. There are (just a few) registers being defined in bcma header. It's because DMU/CRU registers will be also needed in other drivers. We will need them e.g. in PCIe controller/PHY driver and at some point probably in clock driver for BCM53573 chipset. By using include/linux/bcma/ we avoid code duplication. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
4faee9a4 |
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27-Mar-2016 |
Anup Patel <anup.patel@broadcom.com> |
phy: Add support for NS2 SATA3 PHY in Broadcom SATA3 PHY driver This patch adds support for Broadcom NS2 SATA3 PHY in existing Broadcom SATA3 PHY driver. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
53d2a715 |
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11-Nov-2015 |
Thierry Reding <treding@nvidia.com> |
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
037c4189 |
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27-Mar-2016 |
Anup Patel <anup.patel@broadcom.com> |
phy: Rename phy-brcmstb-sata driver to phy-brcm-sata driver Currently, we have a common SATA3 PHY driver for all Broadcom STB SoCs. This driver can be extended and re-used for Broadcom iProc SoCs having same SATA3 PHY. This patch renames existing Broadcom STB SATA3 PHY driver to common Broadcom SATA3 PHY driver to share this PHY driver across Broadcom SoCs. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
fd968973 |
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15-Feb-2016 |
Yakir Yang <kuankuan.y@gmail.com> |
phy: Add driver for rockchip Display Port PHY Add phy driver for the Rockchip DisplayPort PHY module. This is required to get DisplayPort working in Rockchip SoCs. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
c474a949 |
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03-Feb-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
phy: add a driver for the Rockchip SoC internal eMMC PHY This patch to add a generic PHY driver for ROCKCHIP eMMC PHY. Access the PHY via registers provided by GRF (general register files) module. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
30e9a0b2 |
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22-Nov-2015 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
phy: add phy-hi6220-usb Support hi6220 use phy for HiKey board Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
f3b5a8d9 |
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29-Nov-2015 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver This patch adds support for R-Car generation 3 USB2 PHY driver. This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared with the HSUSB (USB2.0 peripheral) device. And each channel has independent registers about the PHYs. So, the purpose of this driver is: 1) initializes some registers of SoC specific to use the {ehci,ohci}-platform driver. 2) detects id pin to select host or peripheral on the channel 0. For now, this driver only supports 1) above. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
882fed73 |
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21-Sep-2015 |
Ray Jui <rjui@broadcom.com> |
phy: cygnus: pcie: Add Cygnus PCIe PHY support This patch adds the PCIe PHY support for the Broadcom PCIe RC interface on Cygnus Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Arun Parameswaran <aparames@broadcom.com> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
dc7f190f |
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28-Sep-2015 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
phy: add usb3.0 phy driver for mt65xx SoCs support usb3.0 phy of mt65xx SoCs Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
cbf919bd |
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09-Jul-2015 |
Joachim Eastwood <manabian@gmail.com> |
phy: add lpc18xx usb otg phy driver Add PHY driver for the internal USB OTG PHY found on NXP LPC18xx and LPC43xx devices. This driver takes care of enabling the PHY in CREG (syscon) and setting the required clock frequency. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
57991eba |
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07-Apr-2015 |
Andrew Bresticker <abrestic@chromium.org> |
PHY: Add driver for Pistachio USB2.0 PHY Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
10d9029b |
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29-May-2015 |
Rob Herring <robh@kernel.org> |
phy: add Marvell HSIC 28nm PHY Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928 SOC. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
603c5f9d |
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29-May-2015 |
Rob Herring <robh@kernel.org> |
phy: Add Marvell USB 2.0 OTG 28nm PHY Add driver for USB 28nm PHY found in Marvell PXA1928 SOC. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
0d486806 |
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20-May-2015 |
Brian Norris <computersforpeace@gmail.com> |
phy: add Broadcom SATA3 PHY driver for Broadcom STB SoCs Supports up to two ports which can each be powered on/off and configured independently. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
1c14905e |
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13-May-2015 |
Heikki Krogerus <heikki.krogerus@linux.intel.com> |
phy: add driver for TI TUSB1210 ULPI PHY TUSB1210 ULPI PHY has vendor specific register for eye diagram tuning. On some platforms the system firmware has set optimized value to it. In order to not loose the optimized value, the driver stores it during probe and restores it every time the PHY is powered back on. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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#
9c3b4430 |
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13-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
phy: Add driver to support individual USB PHYs on sun9i Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different controller. This adds a new driver to support the regular USB PHYs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
609adde8 |
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19-Mar-2015 |
Tony Lindgren <tony@atomide.com> |
phy: Add a driver for dm816x USB PHY Add a minimal driver for dm816x USB. This makes USB work on dm816x without any other changes needed as it can use the existing musb_dsps glue layer for the USB controller. Note that this phy is different from dm814x and am335x. Cc: Bin Liu <binmlist@gmail.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
64d11406 |
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12-Dec-2014 |
Yunzhi Li <lyz@rock-chips.com> |
phy: add a driver for the Rockchip SoC internal USB2.0 PHY This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located in the GRF (general register files) module. Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
ca14ab55 |
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15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for 14nm phy This change adds a support for a 14nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
39e794bf |
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15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for 20nm phy This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
adaafaa3 |
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15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for QUALCOMM Technologies UFS PHY drivers This change adds a generic and common API support for ufs phy QUALCOMM Technologies. This support provides common code and also points to specific phy callbacks to differentiate between different behaviors of frequent use-cases (like power on, power off, phy calibration etc). Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
eee47538 |
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12-Nov-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
phy: add support for USB cluster on the Armada 375 SoC The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
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#
13ebb68c |
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20-Nov-2014 |
Antoine Tenart <atenart@kernel.org> |
phy: add the Berlin USB PHY driver Add the driver driving the Marvell Berlin USB PHY. This allows to initialize the PHY and to use it from the USB driver later. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
2c14e9be |
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04-Nov-2014 |
Gabriel FERNANDEZ <gabriel.fernandez@st.com> |
phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
3f8da2e3 |
|
08-Sep-2014 |
Peter Griffin <peter.griffin@linaro.org> |
phy: phy-stih41x-usb: Add usb phy support for STiH41x SoCs. This driver adds support for USB (1.1 and 2.0) phy for STiH415 and STiH416 System-On-Chips from STMicroelectronics. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
#
89ae1f5d |
|
11-Sep-2014 |
Peter Griffin <peter.griffin@linaro.org> |
phy: phy-stih407-usb: Add usb picoPHY driver found on stih407 SoC family This is the generic phy driver for the picoPHY ports used by the USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
#
1233f59f |
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22-Jul-2014 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
phy: Renesas R-Car Gen2 PHY driver This PHY, though formally being a part of Renesas USBHS controller, contains the UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them channels) to the different USB controllers: channel 0 can be connected to either PCI EHCI/OHCI or USBHS controllers, channel 2 can be connected to PCI EHCI/OHCI or xHCI controllers. This is a new driver for this USB PHY currently already supported under drivers/ usb/phy/. The reason for writing the new driver was the requirement that the multiplexing of USB channels to the controller be dynamic, depending on what USB drivers are loaded, rather than static as provided by the old driver. The infrastructure provided by drivers/phy/phy-core.c seems to fit that purpose ideally. The new driver only supports device tree probing for now. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
#
6e877fed |
|
08-Jul-2014 |
Lee Jones <lee.jones@linaro.org> |
phy: miphy365x: Provide support for the MiPHY356x Generic PHY The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
#
4f6160d4 |
|
16-Jul-2014 |
Kumar Gala <galak@codeaurora.org> |
phy: qcom: Add driver for QCOM IPQ806x SATA PHY Add a PHY driver for uses with AHCI based SATA controller driver on the IPQ806x family of SoCs. Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
942a31b5 |
|
06-Jul-2014 |
Antoine Tenart <atenart@kernel.org> |
phy: add a driver for the Berlin SATA PHY The Berlin SoC has a two SATA ports. Add a PHY driver to handle them. The mode selection can let us think this PHY can be configured to fit other purposes. But there are reasons to think the SATA mode will be the only one usable: the PHY registers are only accessible indirectly through two registers in the SATA range, the PHY seems to be integrated and no information tells us the contrary. For these reasons, make the driver a SATA PHY driver. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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1de990d8 |
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13-Jul-2014 |
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> |
phy: qcom: Add driver for QCOM APQ8064 SATA PHY Add a PHY driver for uses with AHCI based SATA controller driver on the APQ8064 family of SoCs. This patch is a forward port from Qualcomm's v3.4 andriod kernel. Tested on IFC6410 board. CC: Sujit Reddy Thumma <sthumma@codeaurora.org> Tested-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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e379413a |
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03-Jul-2014 |
Jiancheng Xue <xuejiancheng@huawei.com> |
phy: add hix5hd2-sata-phy driver Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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949ccc3a |
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20-Dec-2013 |
Mateusz Krawczuk <mat.krawczuk@gmail.com> |
phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver. Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> [k.debski@samsung.com: cleanup and commit description] [k.debski@samsung.com: make changes accordingly to the mailing list comments] Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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64562e99 |
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14-Apr-2014 |
Pratyush Anand <pratyush.anand@gmail.com> |
phy: Add drivers for PCIe and SATA phy on SPEAr13xx ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys. This also adds proper bindings for miphys. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Tested-by: Mohit Kumar <mohit.kumar@st.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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59025887 |
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13-May-2014 |
Vivek Gautam <gautam.vivek@samsung.com> |
phy: Add new Exynos5 USB 3.0 PHY driver Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Also, created a new header file in linux/mfd/syscon/ for Exynos5 SoCs and put the required PMU offset definitions for the basic available PHYs. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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d1481832 |
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18-Apr-2014 |
Arnd Bergmann <arnd@arndb.de> |
phy: exynos: fix building as a module The top-level phy-samsung-usb2 driver may be configured as a loadable module, which currently causes link errors because of the dependency on the exynos{5250,4x12,4210}_usb2_phy_config symbol. Solving this could be achieved by exporting these symbols, but as the SoC-specific parts of the driver are not currently built as modules, it seems better to just link everything into one module and avoid the need for the export. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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88e670fe |
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07-Mar-2014 |
Loc Ho <lho@apm.com> |
PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. Currently, only external clock and Gen3 SATA mode are supported. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Tuan Phan <tphan@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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14da699b |
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06-Mar-2014 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: rename struct omap_control_usb to struct omap_control_phy Rename struct omap_control_usb to struct omap_control_phy since it can be used to control PHY of USB, SATA and PCIE. Also move the driver and include files under *phy* and made the corresponding changes in the users of phy-omap-control. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Felipe Balbi <balbi@ti.com>
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64bf2b23 |
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05-Mar-2014 |
Kamil Debski <k.debski@samsung.com> |
phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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06fb0137 |
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05-Mar-2014 |
Kamil Debski <k.debski@samsung.com> |
phy: Add new Exynos USB 2.0 PHY driver Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic PHY framework. The driver includes support for the Exynos 4x10 and 4x12 SoC families. Signed-off-by: Kamil Debski <k.debski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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a70143bb |
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03-Mar-2014 |
Kishon Vijay Abraham I <kishon@ti.com> |
drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3 driver in drivers/usb/phy to drivers/phy and also renamed the file to phy-ti-pipe3 since this same driver will be used for SATA PHY and PCIE PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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ba4bdc9e |
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01-Mar-2014 |
Hans de Goede <hdegoede@redhat.com> |
PHY: sunxi: Add driver for sunxi usb phy The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed through a single set of registers. Besides this there are also some other phy related bits which need poking, which are per phy, but shared between the ohci and ehci controllers, so these are also controlled from this new phy driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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bcff4cba |
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02-Mar-2014 |
Yuvaraj Kumar C D <yuvaraj.cd@gmail.com> |
PHY: Exynos: Add Exynos5250 SATA PHY driver This patch adds the SATA PHY driver for Exynos5250.This driver uses the generic PHY framework to deal with SATA PHY.Exynos5250 SATA PHY comprises of CMU and TRSV blocks which are of I2C register Map.So this driver configures the CMU and TRSV block of exynos5250 SATA PHY using i2c. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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e3eae857 |
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17-Dec-2013 |
Andrew Lunn <andrew@lunn.ch> |
Phy: Add a PHY driver for Marvell MVEBU SATA PHY. Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver to control this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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7597fdfc |
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19-Dec-2013 |
Matt Porter <mporter@linaro.org> |
phy: add Broadcom Kona USB2 PHY driver Add a driver for the internal Broadcom Kona USB 2.0 PHY found on the BCM281xx family of SoCs. Signed-off-by: Matt Porter <mporter@linaro.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
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74988e8b |
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16-Oct-2013 |
Jingoo Han <jg1.han@samsung.com> |
phy: Add driver for Exynos DP PHY Add a PHY provider driver for the Samsung Exynos SoC Display Port PHY. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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069d2e26 |
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16-Oct-2013 |
Sylwester Nawrocki <sylvester.nawrocki@gmail.com> |
phy: Add driver for Exynos MIPI CSIS/DSIM DPHYs Add a PHY provider driver for the Samsung S5P/Exynos SoC MIPI CSI-2 receiver and MIPI DSI transmitter DPHYs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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6747caa7 |
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27-Sep-2013 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: phy: twl4030: use the new generic PHY framework Used the generic PHY framework API to create the PHY. For powering on and powering off the PHY, power_on and power_off ops are used. Once the MUSB OMAP glue is adapted to the new framework, the suspend and resume ops of usb phy library will be removed. Also twl4030-usb driver is moved to drivers/phy/. However using the old usb phy library cannot be completely removed because otg is intertwined with phy and moving to the new framework completely will break otg. Once we have a separate otg state machine, we can get rid of the usb phy library. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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5d93d1e7 |
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27-Sep-2013 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: phy: omap-usb2: use the new generic PHY framework Used the generic PHY framework API to create the PHY. Now the power off and power on are done in omap_usb_power_off and omap_usb_power_on respectively. The omap-usb2 driver is also moved to driver/phy. However using the old USB PHY library cannot be completely removed because OTG is intertwined with PHY and moving to the new framework will break OTG. Once we have a separate OTG state machine, we can get rid of the USB PHY library. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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ff764963 |
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27-Sep-2013 |
Kishon Vijay Abraham I <kishon@ti.com> |
drivers: phy: add generic PHY framework The PHY framework provides a set of APIs for the PHY drivers to create/destroy a PHY and APIs for the PHY users to obtain a reference to the PHY with or without using phandle. For dt-boot, the PHY drivers should also register *PHY provider* with the framework. PHY drivers should create the PHY by passing id and ops like init, exit, power_on and power_off. This framework is also pm runtime enabled. The documentation for the generic PHY framework is added in Documentation/phy.txt and the documentation for dt binding can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt Cc: Tomasz Figa <t.figa@samsung.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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