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75b6f648 |
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23-Nov-2020 |
Dave Jiang <dave.jiang@intel.com> |
ntb: intel: add Intel NTB LTR vendor support for gen4 NTB Intel NTB device has custom LTR management that is not compliant with the PCIe standard. Add support to set LTR status triggered by link status change. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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134a8654 |
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05-Jun-2020 |
Dave Jiang <dave.jiang@intel.com> |
ntb: intel: add hw workaround for NTB BAR alignment Add NTB_HWERR_BAR_ALIGN hw errata flag to work around issue where the aligment for the XLAT base must be BAR size aligned rather than 4k page aligned. On ICX platform, the XLAT base can be 4k page size aligned rather than BAR size aligned unlike the previous gen Intel NTB. However, a silicon errata prevented this from working as expected and a workaround is introduced to resolve the issue. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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ebb09b33 |
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12-Feb-2019 |
Leonid Ravich <lravich@gmail.com> |
NTB: add new parameter to peer_db_addr() db_bit and db_data NTB door bell usage depends on NTB hardware. ex: intel NTB gen1 has one peer door bell register which can be controlled by the bitmap writen to it, while Intel NTB gen3 has a registers per door bell and the data trigering the each door bell is always 1. therefore exposing only peer door bell address forcing the user to be aware of such low level details Signed-off-by: Leonid Ravich <Leonid.Ravich@emc.com> Acked-by: Logan Gunthorpe <logang@deltatee.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Allen Hubbe <allenbh@gmail.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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f6e51c35 |
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29-Jan-2018 |
Dave Jiang <dave.jiang@intel.com> |
ntb: intel: split out the gen3 code Move the Intel hw gen3 code to its own source file. The ntb_hw_intel.c was getting too large and makes it hard to maintain with future hardware changes. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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a9065055 |
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29-Jan-2018 |
Dave Jiang <dave.jiang@intel.com> |
ntb: intel: header definitions refactor Break out the generation specific definitions to different headers Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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