wifi: rtw89: 8852c: read RX gain offset from efuse for 6GHz channels

Read calibration values of RX gain offset from efuse, and set them to
registers to normalize RX gain for all hardware modules. Then, PHY dynamic
mechanism can get expected values to adjust hardware parameters to yield
expected performance.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231117024029.113845-5-pkshih@realtek.com

wifi: rtw89: phy: make generic txpwr setting functions

Previously, we thought control registers or setting things for TX power
series may change according to chip. So, setting functions are implemented
chip by chip. However, until now, the functions keep the same among chips,
at least 8852A, 8852C, and 8852B. There is a sufficient number of chips to
share generic setting functions. So, we now remake them including TX power
by rate, TX power offset, TX power limit, and TX power limit RU as generic
ones in phy.c.

Besides, there are some code refinements in the generic ones, but almost
all of the logic doesn't change.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220928084336.34981-5-pkshih@realtek.com

rtw89: 8852c: implement chip_ops related to TX power

Three chip_ops are implemented in this patch. The ::set_txpwr_ctrl and
::init_txpwr_unit are called when we up interface and then configure TX
power registers to initial values. The ::set_txpwr_ctrl is to configure
'txpwr_ref' to make basic output TX power of OFDM and CCK rate to be the
same. The ::init_txpwr_unit is to initialize TSSI (a method to do TX power
compensation depends on thermal value) control and bandedge.

The ::set_txpwr is called once switching channel. First, it sets TX power
for each rate section (e.g. CCK, OFDM), and then sets TX power offset
between 1SS and 2SS rate. Finally, it sets TX power limit to prevent
power over regulation.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220421120903.73715-12-pkshih@realtek.com

rtw89: 8852c: add efuse gain offset parser

Define efuse struct to access gain offset, and store them for further use
by setting channel.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220414062027.62638-8-pkshih@realtek.com

rtw89: 8852c: support bb gain info

Add parser for bb gain table and configure bb gain table for 8852c.
While ctrl_ch, obtain bb gain error settings and write them to phy.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220414062027.62638-7-pkshih@realtek.com

rtw89: 8852c: process logic efuse map

Add a struct to access logic efuse map, and fill data according to the map.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220307060457.56789-14-pkshih@realtek.com

rtw89: 8852c: process efuse of phycap

Read phycap data programmed in efuse, and store them into array.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220307060457.56789-13-pkshih@realtek.com

rtw89: 8852c: add 8852c empty files

Add these files, and then I can add specific chip::ops or chip::info along
with the existing chip.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220307060457.56789-2-pkshih@realtek.com