History log of /linux-master/drivers/net/wireless/realtek/rtw89/rtw8852be.c
Revision Date Author Comments
# 0bc7d1d4 21-Jan-2024 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: validate RX tag for RXQ and RPQ

PCI RX ring is a kind of read/write index ring, and DMA and ring index are
asynchronous, so suddenly driver gets newer index ahead before DMA. To
resolve this rare situation, we use a RX tag as helpers to make sure DMA
is done.

The RX tag is a 13-bit value, and range is from 1 ~ 0x1FFF, but 0 isn't
used so should be skipped.

Only enable this validation to coming WiFi 7 chips, because existing
chips use different design and don't really meet this situation.

Add missed rx_ring_eq_is_full for 8851BE by the way.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20240121071826.10159-4-pkshih@realtek.com


# 9f08c77b 09-Nov-2023 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: correct interrupt mitigation register for 8852CE

To reduce interrupt count, configure mitigation register with thresholds
of time and packet count. We missed that 8852CE uses different register
address, so correct it. Then, interrupt counts down to 30,763 from 229,825
during stress test in 20 seconds.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231110012319.12727-7-pkshih@realtek.com


# 07fabde6 01-Nov-2023 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: add PCI generation information to pci_info for each chip

In order to reuse PCI initial and configuration flows, add struct
rtw89_pci_gen_def to abstract the differences between WiFi 6/7 generations.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231101072149.21997-2-pkshih@realtek.com


# 58534b3b 26-Oct-2023 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: generalize code of PCI control DMA IO for WiFi 7

The register to enable/disable PCI DMA IO has many variants, so define
and use a field to control it accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231026120049.9187-5-pkshih@realtek.com


# 0dc93242 26-Oct-2023 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: add new RX ring design to determine full RX ring efficiently

To make hardware efficient to determine if RX ring is full, introduce new
design that checks if reading and writing indices are equal. Comparing
to old design, initial indices of both reading and writing indices are 0
that means empty, and hardware checks full by "writing index + 1 ==
reading index". The "+1" has extra cost for hardware, so new design is
to avoid this.

Take ring size is 256 as an example, the initial reading and writing
indices are 255 and 0 respectively; the initial values mean empty. If two
indices are the same, for example 5 and 5, it means ring is full.

wp rp used_cnt state
255 0 0 initial (ring is empty)
255 1 1 receive 1st packet
255 2 2 receive 2nd packet
0 2 1 driver read 1st packet
1 2 0 driver read 2nd packet (ring is empty)
:
5 5 255 ring is full

Note: 'rp' is hardware writing index

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231026120049.9187-4-pkshih@realtek.com


# 7f495de6 13-Jan-2023 Zong-Zhe Yang <kevin_yang@realtek.com>

wifi: rtw89: fix assignation of TX BD RAM table

TX BD's RAM table describes how HW allocates usable buffer section
for each TX channel at fetch time. The total RAM size for TX BD is
chip-dependent. For 8852BE, it has only half size (32) for TX channels
of single band. Original table arrange total size (64) for dual band.
It will overflow on 8852BE circuit and cause section conflicts between
different TX channels.

So, we do the changes below.
* add another table for single band chip and export both kind of tables
* point to the expected one in rtw89_pci_info by chip

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230113090632.60957-4-pkshih@realtek.com


# 9695dc2e 28-Sep-2022 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: 8852be: add 8852BE PCI entry

8852BE has two variants with different ID. One is 10ec:b852 that is a main
model with 2x2 antenna, and the other is 10ec:b85b that is a 1x1 model.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220928084336.34981-10-pkshih@realtek.com


# 61bdf7aa 27-Sep-2022 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: add DMA busy checking bits to chip info

8852B has less DMA channels, so its checking bits are different from other
chips.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-4-pkshih@realtek.com


# 1bebcf08 27-Sep-2022 Ping-Ke Shih <pkshih@realtek.com>

wifi: rtw89: pci: mask out unsupported TX channels

8852BE doesn't support some TX channels, so mask them out, or it access
undefined registers.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-2-pkshih@realtek.com