#
0bc7d1d4 |
|
21-Jan-2024 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: validate RX tag for RXQ and RPQ PCI RX ring is a kind of read/write index ring, and DMA and ring index are asynchronous, so suddenly driver gets newer index ahead before DMA. To resolve this rare situation, we use a RX tag as helpers to make sure DMA is done. The RX tag is a 13-bit value, and range is from 1 ~ 0x1FFF, but 0 isn't used so should be skipped. Only enable this validation to coming WiFi 7 chips, because existing chips use different design and don't really meet this situation. Add missed rx_ring_eq_is_full for 8851BE by the way. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240121071826.10159-4-pkshih@realtek.com
|
#
9f08c77b |
|
09-Nov-2023 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: correct interrupt mitigation register for 8852CE To reduce interrupt count, configure mitigation register with thresholds of time and packet count. We missed that 8852CE uses different register address, so correct it. Then, interrupt counts down to 30,763 from 229,825 during stress test in 20 seconds. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231110012319.12727-7-pkshih@realtek.com
|
#
07fabde6 |
|
01-Nov-2023 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: add PCI generation information to pci_info for each chip In order to reuse PCI initial and configuration flows, add struct rtw89_pci_gen_def to abstract the differences between WiFi 6/7 generations. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231101072149.21997-2-pkshih@realtek.com
|
#
58534b3b |
|
26-Oct-2023 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: generalize code of PCI control DMA IO for WiFi 7 The register to enable/disable PCI DMA IO has many variants, so define and use a field to control it accordingly. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231026120049.9187-5-pkshih@realtek.com
|
#
0dc93242 |
|
26-Oct-2023 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: add new RX ring design to determine full RX ring efficiently To make hardware efficient to determine if RX ring is full, introduce new design that checks if reading and writing indices are equal. Comparing to old design, initial indices of both reading and writing indices are 0 that means empty, and hardware checks full by "writing index + 1 == reading index". The "+1" has extra cost for hardware, so new design is to avoid this. Take ring size is 256 as an example, the initial reading and writing indices are 255 and 0 respectively; the initial values mean empty. If two indices are the same, for example 5 and 5, it means ring is full. wp rp used_cnt state 255 0 0 initial (ring is empty) 255 1 1 receive 1st packet 255 2 2 receive 2nd packet 0 2 1 driver read 1st packet 1 2 0 driver read 2nd packet (ring is empty) : 5 5 255 ring is full Note: 'rp' is hardware writing index Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231026120049.9187-4-pkshih@realtek.com
|
#
7f495de6 |
|
13-Jan-2023 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
wifi: rtw89: fix assignation of TX BD RAM table TX BD's RAM table describes how HW allocates usable buffer section for each TX channel at fetch time. The total RAM size for TX BD is chip-dependent. For 8852BE, it has only half size (32) for TX channels of single band. Original table arrange total size (64) for dual band. It will overflow on 8852BE circuit and cause section conflicts between different TX channels. So, we do the changes below. * add another table for single band chip and export both kind of tables * point to the expected one in rtw89_pci_info by chip Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230113090632.60957-4-pkshih@realtek.com
|
#
61bdf7aa |
|
27-Sep-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: add DMA busy checking bits to chip info 8852B has less DMA channels, so its checking bits are different from other chips. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220927062611.30484-4-pkshih@realtek.com
|
#
1bebcf08 |
|
27-Sep-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: pci: mask out unsupported TX channels 8852BE doesn't support some TX channels, so mask them out, or it access undefined registers. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220927062611.30484-2-pkshih@realtek.com
|
#
5280e481 |
|
12-Sep-2022 |
Chin-Yen Lee <timlee@realtek.com> |
wifi: rtw89: pci: concentrate control function of TX DMA channel Different chips use different register and mask for tx dma channels, so concentrate them. Signed-off-by: Chin-Yen Lee <timlee@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220912071706.13619-4-pkshih@realtek.com
|
#
52edbb9f |
|
21-Apr-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: ps: access TX/RX rings via another registers in low power mode In low power mode, we need to pause PCI to configure IMR and PCI ring index registers accordingly, because the regular registers are power-off in this mode. In the transition moment named paused in code, we can't touch ring index, so don't kick off DMA immediately. Instead, queue them into pending queue, and kick off after the moment. There are three low power modes, which are RF off/clock gate/power gate, but PCI enter low power mode in later two modes only. So, add a mask to achieve this. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220421120903.73715-7-pkshih@realtek.com
|
#
e1757e80 |
|
21-Apr-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add variant RPWM/CPWM to enter low power mode RPWM/CPWM are registers that can set and check low power mode. Since chips use different address, add a field to access them in common flow. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220421120903.73715-3-pkshih@realtek.com
|
#
948e521c |
|
21-Apr-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add variant IMR/ISR and configure functions 8852CE uses different but similar IMR/ISR registers, and its masks are also different in various states, so add config_intr_mask ops to configure masks according to under_recovery or low_power states. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220421120903.73715-2-pkshih@realtek.com
|
#
0db862fb |
|
25-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add LTR setting for v1 chip Add LTR handle to PCI deinit as well. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-5-pkshih@realtek.com
|
#
1e3f2055 |
|
25-Mar-2022 |
Chia-Yuan Li <leo.li@realtek.com> |
rtw89: pci: refine pci pre_init function The pre_init is used to initialize partial PCI function during PCI probe. It doesn't need to initialize all functions, so probe can be faster. Signed-off-by: Chia-Yuan Li <leo.li@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-4-pkshih@realtek.com
|
#
b9467e94 |
|
25-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add pci attributes to configure operating mode Refine operating mode function to support variant chips. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-3-pkshih@realtek.com
|
#
740c431c |
|
25-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add register definition to rtw89_pci_info to generalize pci code The PCI code of 8852AE and 8852CE are different, but the flow and register names are similar. To reuse the code, add a struct to define register or value accordingly. We also use chip id to control the slightly different flow. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-2-pkshih@realtek.com
|
#
6d5b5d62 |
|
17-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: support variant of fill_txaddr_info The txaddr_info is used to fill the DMA address of skb->data. The v1 version can support up to 10 entries, but the maximum size of each entry is 2047, so it fill more than one entry for large packet, like 3000 bytes. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220318023214.32411-9-pkshih@realtek.com
|
#
97d61bf9 |
|
06-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add V1 of PCI channel address 8852CE use V1 address, and flow is totally shared with 8852AE. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220307060457.56789-4-pkshih@realtek.com
|
#
4a9e48ac |
|
06-Mar-2022 |
Ping-Ke Shih <pkshih@realtek.com> |
rtw89: pci: add struct rtw89_pci_info Use this struct to implement chip::ops related to PCI interface. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220307060457.56789-3-pkshih@realtek.com
|
#
861e58c8 |
|
20-Dec-2021 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
rtw89: extract modules by chipset We are planning to support more chipsets, e.g. 8852C. Before that, we consider architecutre to handle multiple kinds of chipsets. Obviosuly, based on original design, rtw89_core module will have large size even if there is only one chipset under running. It is because all chipset related things are put in rtw89_core now. To reduce such overhead, we extract modules of rtw89 and adjust dependencies between modules. The following assumes that 8852AE, 8852AU, and 8852CE are all supported, we describe the difference before and after extraction. [Before extraction] ------------- |------------------------------------ | rtw89_usb | V ------------- --------------------------------------- ------------- | rtw89_core (including 8852A, 8852C) | <--- | rtw89_pci | --------------------------------------- ------------- The data of 8852A and 8852C are built in rtw89_core. And rtw89_pci is the entry of 8852AE and 8852CE. And rtw89_usb is the entry of 8852AU. [After extraction] ------------- ---------------- |----------- | rtw89_usb | <-------- | rtw89_8852au | | ------------- ---------------- V --------------- | -------------- | | <--------------- | rtw89_core | <--- | rtw89_8852a | -------------- | | <--------------- ^ ^ --------------- | | | ------------- ---------------- | | | | <-------- | rtw89_8852ae | | |----------- | rtw89_pci | ---------------- | | | <----------------- | ------------- | | --------------- ---------------- |--------------- | rtw89_8852c | <------ | rtw89_8852ce | --------------- ---------------- The data of 8852A/8852C is extracted to rtw89_8852a/rtw89_8852c. And rtw89_pci/rtw89_usb handles only common flow of pci/usb bus. Finally, 8852AE, 8852AU, and 8852CE have individual entry modules, i.e. rtw89_8852ae, rtw89_8852au, and rtw89_8852ce correspondingly. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20211221025828.25092-1-pkshih@realtek.com
|