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155b10ab |
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01-Apr-2024 |
Kuan-Chung Chen <damon.chen@realtek.com> |
wifi: rtw89: 8922a: configure UL MU/OFDMA power setting 8922A needs to set UL MU/OFDMA power and fine tune power error tolerance for proper response to AP's trigger frame. Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://msgid.link/20240401063818.12880-1-pkshih@realtek.com
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db84b758 |
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08-Feb-2024 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: correct PHY register offset for PHY-1 PHY-1 can be seen as a copy of PHY-0, and the difference is their base register address, so add a function to get offset to access PHY-1. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240209065229.34515-2-pkshih@realtek.com
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6bd23219 |
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04-Jan-2024 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: phy: set channel_info for WiFi 7 chips The channel_info is hardware settings to reflect operational status, such as scale factor, report unit, buffer matrix size, RU size and so on. Then, we can get desired reports to do further tuning. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240105064440.36926-1-pkshih@realtek.com
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ce84ecbd |
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04-Jan-2024 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: phy: add BB wrapper of TX power for WiFi 7 chips TX power is controlled by BB layer basically, but it should interact with MAC layer, so these registers are put on MAC register domain and called BB wrapper, which contains TX power for each MAC ID, OFDMA RU power, and consideration of power type table. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240105064433.36870-1-pkshih@realtek.com
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c207e14d |
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04-Jan-2024 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: 8922a: add NCTL pre-settings for WiFi 7 chips NCTL standing for nano-controller is used to assist RF calibration. Basically, we write settings from a table, but format of the table can't describe register mask and additional conditions, so add a function to set this kind of settings. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240105064422.36812-1-pkshih@realtek.com
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0edcdd82 |
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04-Jan-2024 |
Chung-Hsuan Hung <hsuan8331@realtek.com> |
wifi: rtw89: phy: add parser to support RX gain dynamic setting flow Add RX gain offset dynamic setting flow according to different bands and bandwidths. RX gain offset values will be different according to different channel bands, therefore, this dynamic mechanism is needed while channel is changed. Add this to parse data from the element of firmware file, and then we can use them easier at runtime. Signed-off-by: Chung-Hsuan Hung <hsuan8331@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240105064228.36580-3-pkshih@realtek.com
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5d2f3c3a |
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16-Oct-2023 |
Cheng-Chieh Hsieh <cj.hsieh@realtek.com> |
wifi: rtw89: modify the register setting and the flow of CFO tracking The register address used for CFO(carrier frequency offset) tracking is different from WiFi 7 series, so we change the way to access it. And we refine the flow of CFO tracking to compatible all WiFi 7 and 6 ICs. Signed-off-by: Cheng-Chieh Hsieh <cj.hsieh@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231016065115.751662-4-pkshih@realtek.com
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932f85c1 |
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02-Oct-2023 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
wifi: rtw89: phy: set TX power RU limit according to chip gen Wi-Fi 6 chips and Wi-Fi 7 chips have different register design for TX power RU limit. We rename original setting stuffs with a suffix `_ax`, concentrate related enum declaration in phy.h, and implement setting flow for Wi-Fi 7 chips. Then, we set TX power RU limit according to chip generation. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231003015446.14658-6-pkshih@realtek.com
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70aa04f2 |
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02-Oct-2023 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
wifi: rtw89: phy: set TX power limit according to chip gen Wi-Fi 6 chips and Wi-Fi 7 chips have different register design for TX power limit. We rename original setting stuffs with a suffix `_ax`, concentrate related enum declaration in phy.h, and implement setting flow for Wi-Fi 7 chips. Then, we set TX power limit according to chip generation. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231003015446.14658-5-pkshih@realtek.com
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3b7dc652 |
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02-Oct-2023 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
wifi: rtw89: phy: set TX power offset according to chip gen We have a register to control TX power of each rate section to increase or decrease an offset. But, Wi-Fi 6 chips and Wi-Fi 7 chips have different address and format for this control register. We rename original setting stuffs with a suffix `_ax` and implement setting flow for Wi-Fi 7 chips. Then, we set TX power offset according to chip generation. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231003015446.14658-4-pkshih@realtek.com
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d5136642 |
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02-Oct-2023 |
Zong-Zhe Yang <kevin_yang@realtek.com> |
wifi: rtw89: phy: set TX power by rate according to chip gen Wi-Fi 6 chips and Wi-Fi 7 chips have different register design for TX power by rate. We rename original setting stuffs with a suffix `_ax` and implement setting flow for Wi-Fi 7 chips. Then, we set TX power by rate according to chip generation. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231003015446.14658-3-pkshih@realtek.com
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058b2074 |
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22-Aug-2023 |
Cheng-Chieh Hsieh <cj.hsieh@realtek.com> |
wifi: rtw89: phy: modify register setting of ENV_MNTR, PHYSTS and DIG The ENV_MNTR(environment monitor) is the dynamic mechanism which based on the HW of CCX(Cisco Compatible Extensions) which provide the channel loading and noisy level indicator to debug or support the 802.11k. The PHYSTS provide the detail PHY information per packet we received for debugging. The DIG(dynamic initial gain) is the dynamic mechanism to adjust the packet detect power level by received signal strength to avoid false detection of the WiFi packet. The address of registers used for ENV_MNTR, PHYSTS and DIG of WiFi 7 IC are different with WiFi 6 series, so we modify the method to access the register address in order to compatible with all WiFi 7 and 6 ICs. Signed-off-by: Cheng-Chieh Hsieh <cj.hsieh@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230822125822.23817-7-pkshih@realtek.com
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1165f571 |
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22-Aug-2023 |
Ping-Ke Shih <pkshih@realtek.com> |
wifi: rtw89: phy: add phy_gen_def::cr_base to support WiFi 7 chips cr_base is base address of PHY control register. The base of WiFi 6 and 7 chips are 0x1_0000 and 0x2_0000 respectively, so define them accordingly. For example, if PHY address is 0x1330, absolute address is 0x1_1330 for WiFi 6 chips, and 0x2_1330 for WiFi 7 chips. Meanwhile, there are two copies of PHY hardware named PHY0 and PHY1. The offset between them is 0x2_0000, so the base address of PHY0 and PHY1 are 0x2_0000 and 0x4_0000 respectively. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230822125822.23817-6-pkshih@realtek.com
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