#
24a1720a |
|
08-Feb-2021 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect serial config version from register Collect serial config version information directly from an internal register, instead of explicitly resizing VPD. v2: - Add comments on info stored in PCIE_STATIC_SPARE2 register. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cca85283 |
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24-Aug-2020 |
Raju Rangoju <rajur@chelsio.com> |
cxgb4: add error handlers to LE intr_handler cxgb4 does not look for HASHTBLMEMCRCERR and CMDTIDERR bits in LE_DB_INT_CAUSE register, but these are enabled in LE_DB_INT_ENABLE. So, add error handlers to LE interrupt handler to emit a warning or alert message for hash table mem crc and cmd tid errors Signed-off-by: Raju Rangoju <rajur@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d915c299 |
|
19-Jun-2020 |
Vishal Kulkarni <vishal@chelsio.com> |
cxgb4: add skeleton for ethtool n-tuple filters Allocate and manage resources required for ethtool n-tuple filters. Also fetch the HASH filter region size and calculate nhash entries. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
55088355 |
|
18-Jun-2020 |
Vishal Kulkarni <vishal@chelsio.com> |
cxgb4: add support to flash boot image Update set_flash to flash boot image to flash region Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
bd019427 |
|
20-Apr-2020 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: fix large delays in PTP synchronization Fetching PTP sync information from mailbox is slow and can take up to 10 milliseconds. Reduce this unnecessary delay by directly reading the information from the corresponding registers. Fixes: 9c33e4208bce ("cxgb4: Add PTP Hardware Clock (PHC) support") Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1f074e67 |
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25-Mar-2020 |
Rahul Kundu <rahul.kundu@chelsio.com> |
cxgb4: Add support to catch bits set in INT_CAUSE5 This commit adds support to catch any bits set in SGE_INT_CAUSE5 for Parity Errors. F_ERR_T_RXCRC flag is used to ignore that particular bit as it is not considered as fatal. So, we clear out the bit before looking for error. This patch now read and report separately all three registers(Cause1, Cause2, Cause5). Also, checks for errors if any. Signed-off-by: Raju Rangoju <rajur@chelsio.com> Signed-off-by: Rahul Kundu <rahul.kundu@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
74dd5aa1 |
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22-May-2019 |
Vishal Kulkarni <vishal@chelsio.com> |
cxgb4: Enable hash filter with offload Hash (exact-match) filters used for offloading flows share the same active region resources on the chip with upper layer drivers, like iw_cxgb4, chcr, etc. Currently, only either Hash filters or ULDs can use the active region resources, but not both. Hence, use the new firmware configuration parameters (when available) to allow both the Hash filters and ULDs to share the active region simultaneously. Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9d0f180c |
|
24-Jul-2018 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect number of free PSTRUCT page pointers Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fa145d5d |
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18-Jul-2018 |
Ganesh Goudar <ganeshgr@chelsio.com> |
cxgb4: display number of rx and tx pages free display free rx and tx page count in the meminfo of an adapter. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1eb94d44 |
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16-Jul-2018 |
Surendra Mobiya <surendra@chelsio.com> |
cxgb4: collect ASIC LA dumps from ULP TX Signed-off-by: Surendra Mobiya <surendra@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8e725f7c |
|
16-May-2018 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: update LE-TCAM collection for T6 For T6, clip table is separated from main TCAM. So, update LE-TCAM collection logic to collect clip table TCAM as well. IPv6 takes 4 entries in clip table TCAM compared to 2 entries in main TCAM. Also, in case of errors, keep LE-TCAM collected so far and set the status to partial dump. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
98f3697f |
|
14-May-2018 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: add tc flower match support for tunnel VNI Adds support for matching flows based on tunnel VNI value. Introduces fw APIs for allocating/removing MPS entries related to encapsulation. And uses the same while adding/deleting filters for offloading flows based on tunnel VNI match. Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e1087089 |
|
31-Mar-2018 |
Atul Gupta <atul.gupta@chelsio.com> |
cxgb4: Inline TLS FW Interface Key area size in hw-config file. CPL struct for TLS request and response. Work request for Inline TLS. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Reviewed-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c746fc0e |
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22-Jan-2018 |
Ganesh Goudar <ganeshgr@chelsio.com> |
cxgb4: add geneve offload support for T6 Add geneve segmentation offload support of T6 cards. Original work by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ef0fd85a |
|
10-Jan-2018 |
Ganesh Goudar <ganeshgr@chelsio.com> |
cxgb4: add data structures to support vxlan Add data structures and macros to be used in vxlan offload. Original work by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
be6e36d9 |
|
01-Jan-2018 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect TX rate limit info in UP CIM logs Collect TX rate limiting related information in UP CIM logs. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4db0401f |
|
07-Dec-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect HMA memory dump Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9e5c598c |
|
11-Nov-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect SGE queue context dump Collect SGE freelist queue and congestion manager contexts. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
03e98b91 |
|
11-Nov-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect LE-TCAM dump Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5c31254e |
|
31-Oct-2017 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: initialize hash-filter configuration Add support for hash-filter configuration on T6. Also, do basic checks for the related initialization. Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0ba9a3b6 |
|
31-Oct-2017 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: save additional filter tuple field shifts in tp_params Save additional filter tuple field shifts in tp_params based on configured filter tuple fields. Also, save the combined filter tuple mask based on configured filter tuple fields. Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
08c4901b |
|
26-Oct-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect hardware scheduler dumps Collect hardware TX traffic scheduler and pace tables. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b289593e |
|
26-Oct-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect MPS-TCAM dump Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9030e498 |
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26-Oct-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect TID info dump Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
27887bc7 |
|
26-Oct-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect hardware LA dumps Collect CIM, CIM_MA, ULP_RX, TP, CIM_PIF, and ULP_TX logic analyzer dumps. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4359cf33 |
|
13-Oct-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: collect TP dump Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a4569504 |
|
04-Jul-2017 |
Atul Gupta <atul.gupta@chelsio.com> |
cxgb4: time stamping interface for PTP Supports hardware and software time stamping via the Linux SO_TIMESTAMPING socket option. Cc: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d86cc04e |
|
08-Jun-2017 |
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> |
cxgb4: handle interrupt raised when FW crashes Handle TIMER0INT when FW crashes. Check for PCIE_FW[FW_EVAL] and if it says "Device FW Crashed", then treat it as fatal. Else, non-fatal. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3be0679b |
|
13-Jan-2017 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Shutdown adapter if firmware times out or errors out Perform an emergency shutdown of the adapter and stop it from continuing any further communication on the ports or DMA to the host. This is typically used when the adapter and/or firmware have crashed and we want to prevent any further accidental communication with the rest of the world. This will also force the port Link Status to go down -- if register writes work -- which should help our peers figure out that we're down. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f750e82e |
|
13-Jan-2017 |
Ganesh Goudar <ganeshgr@chelsio.com> |
cxgb4: Fix misleading packet/frame count stats. Do not count pause frames as part of general TX/RX frame counters. Based on the original work of Casey Leedom <leedom@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8eb9f2f9 |
|
04-Jan-2017 |
Arjun V <arjun@chelsio.com> |
cxgb4: Support compressed error vector for T6 t6fw-1.15.15.0 enabled compressed error vector in cpl_rx_pkt for T6. Updating driver to take care of these changes. Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Arjun V <arjun@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
115b56af |
|
23-Dec-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Update mps_tcam output to include T6 fields In T6, MPS classification has a 512 deep TCAM to do the match lookup. Each entry has 80x2b sets containing 48 bit MAC address, port number, VLAN Valid/ID, VNI, lookup type (outer or inner packet header). [71:48] bit locations are overloaded for outer vs. inner lookup types. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
676d6a75 |
|
23-Dec-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Update register range and SGE registers for T6 adapter Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
eb72f74f |
|
09-Dec-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Handle clip return values Add a warn message when clip table overflows. If clip table isn't allocated, return from cxgb4_clip_release() to avoid panic. Disable offload if clip isn't enabled in the hardware. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8e3d04fd |
|
12-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add MPS tracing support Handle TRACE_PKT, stack can sniff them on the first port Add debubfs enrty to configure tracing for offload traffic like iWARP & iSCSI for debugging purpose. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a4011fd4 |
|
12-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add debugfs support to dump tid info Add debugfs support to dump tid info like stid, sftid, tids, atid and hwtids Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9a1bb9f6 |
|
12-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Differentiates between TIDs being used in TCAM and HASH For the tid info, differentiate from which region the TID is allocated from. It can be from TCAM region or HASH region. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d86bd29e |
|
04-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf: read the correct bits of PL Who Am I register Read the correct bits of PL Who Am I for the Source PF field which has changed in T6 Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bf8ebb67 |
|
04-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support to dump edc bist status Add support to dump edc bist status for ECC data errors Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5888111c |
|
04-Aug-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add debugfs support to dump meminfo Add debug support to dump memory address ranges of various hardware modules of the adapter. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ea6f82fe |
|
23-Jul-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4vf: Read correct FL congestion threshold for T5 and T6 VF driver was reading incorrect freelist congestion notification threshold for FLM queues when packing is enabled for T5 and T6 adapter. Fixing it now. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7864026b |
|
09-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add debugfs entry to dump channel rate Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
19689609 |
|
09-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add debugfs entry to dump CIM PIF logic analyzer contents Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
26fae93f |
|
09-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add a debugfs entry to dump CIM MA logic analyzer logs Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
65046e84 |
|
03-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support to dump loopback port stats Add support in ethtool to dump loopback port statistics Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a6222975 |
|
03-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support in ethtool to dump channel stats Add support in ethtool to dump adapter channel stats Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a4cfd929 |
|
03-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add ethtool support to get adapter stats Add ethtool support to get adapter specific hardware statistics Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3ccc6cf7 |
|
02-Jun-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Adds support for T6 adapter Adds NIC driver related changes for T6 adapter. Register related changes, MC related changes, VF related changes, doorbell related changes, debugfs changes, etc Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ae469b68 |
|
01-Apr-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Fix to dump devlog, even if FW is crashed Add new Common Code routines to retrieve Firmware Device Log parameters from PCIE_FW_PF[7]. The firmware initializes its Device Log very early on and stores the parameters for its location/size in that register. Using the parameters from the register allows us to access the Firmware Device Log even when the firmware crashes very early on or we're not attached to the firmware Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bad43792 |
|
06-Feb-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support in debugfs to dump the congestion control table Dump Transport Processor modules congestion control configuration Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bf7c781d |
|
06-Feb-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support to dump mailbox content in debugfs Adds support to dump the current contents of mailbox and the driver which owns it. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
797ff0f5 |
|
06-Feb-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support for ULP RX logic analyzer output in debugfs Dump Upper Layer Protocol RX module command trace Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
2d277b3b |
|
06-Feb-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Added support in debugfs to display TP logic analyzer output Dump Transport Processor event trace. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b58b6676 |
|
27-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Added support in debugfs to dump different timer and clock values of the adapter Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b3bbe36a |
|
27-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Added support in debugfs to dump PM module stats Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c778af7d |
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27-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Addded support in debugfs to dump CIM outbound queue content Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e5f0e43b |
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27-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Added support in debugfs to dump cim ingress bound queue contents Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
688ea5fe |
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19-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add debugfs options to dump the rss key, config for PF, VF, etc Adds support to dump the rss table, rss_config, rss_key, rss_pf_config and rss_vf_config Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ef82f662 |
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06-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support for mps_tcam debugfs Debug log to get the MPS TCAM table Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
74b3092c |
|
06-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support for cim_qcfg entry in debugfs Adds debug log to get cim queue config Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f1ff24aa |
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06-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support for cim_la entry in debugfs The CIM LA captures the embedded processor’s internal state. Optionally, it can also trace the flow of data in and out of the embedded processor. Therefore, the CIM LA output contains detailed information of what code the embedded processor executed prior to the CIM LA capture. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
0d804338 |
|
05-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf/csiostor: Cleanup PL, XGMAC, SF and MC related register defines This patch cleanups all PL, XGMAC and SF related macros/register defines that are defined in t4_regs.h and the affected files Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
837e4a42 |
|
05-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/csiostor: Cleanup TP, MPS and TCAM related register defines This patch cleanups all TP, MPS and TCAM related macros/register defines that are defined in t4_regs.h and the affected files Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
89c3a86c |
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05-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxg4vf/csiostor: Cleanup MC, MA and CIM related register defines This patch cleanups all MC, MA and CIM related macros/register defines that are defined in t4_regs.h and the affected files. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f061de42 |
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05-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf/csiostor: Cleanup SGE and PCI related register defines This patch cleansup remaining SGE related macros/register defines and all PCI related ones that are defined in t4_regs.h and the affected files. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f612b815 |
|
05-Jan-2015 |
Hariprasad Shenai <hariprasad@chelsio.com> |
RDMA/cxgb4/cxgb4vf/csiostor: Cleanup SGE register defines This patch cleanups all SGE related macros/register defines that are defined in t4_regs.h and the affected files. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e85c9a7a |
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03-Dec-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf: Add code to calculate T5 BAR2 Offsets for SGE Queue Registers Add new Common Code facilities for calculating T5 BAR2 Offsets for SGE Queue Registers. This new code can handle situations where Queues Per Page * SGE BAR2 Queue Register Area Size > Page Size Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e0a8b34a |
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03-Dec-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4vf: Add and initialize some sge params for VF driver Add sge_vf_eq_qpp and sge_vf_iq_qpp to (struct sge_params), initialize sge_queues_per_page and sge_vf_qpp in t4vf_get_sge_params(), add new t4vf_prep_adapter() which initializes basic adapter parameters. Grab both SGE_EGRESS_QUEUES_PER_PAGE_VF and SGE_INGRESS_QUEUES_PER_PAGE_VF for VF Drivers since we need both to calculate the User Doorbell area offsets for Egress and Ingress Queues. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ce8f407a |
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07-Nov-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers T5 introduces the ability to have separate Packing and Padding Boundaries for SGE DMA transfers from the chip to Host Memory. This change set takes advantage of that to set up a smaller Padding Boundary to conserve PCI Link and Memory Bandwidth with T5. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6559a7e8 |
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06-Nov-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Cleanup macros so they follow the same style and look consistent Various patches have ended up changing the style of the symbolic macros/register to different style. As a result, the current kernel.org files are a mix of different macro styles. Since this macro/register defines is used by different drivers a few patch series have ended up adding duplicate macro/register define entries with different styles. This makes these register define/macro files a complete mess and we want to make them clean and consistent. This patch cleans up a part of it. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7207c0d1 |
|
08-Oct-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/cxgb4vf: Updated the LSO transfer length in CPL_TX_PKT_LSO for T5 Update the lso length for T5 adapter and fix PIDX_T5 macro Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e553ec3f |
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25-Sep-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add support for adaptive rx Based on original work by Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d63a6dcf |
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25-Sep-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Use BAR2 Going To Sleep (GTS) for T5 and later. Use BAR2 GTS for T5. If we are on T4 use the old doorbell mechanism; otherwise ue the new BAR2 mechanism. Use BAR2 doorbells for refilling FL's. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9bb59b96 |
|
01-Sep-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Fix T5 adapter accessing T4 adapter registers Fixes few register access for both T4 and T5. PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2 is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use MPS_T5_TRC_RSS_CONTROL. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
822dd8a8 |
|
21-Jul-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Add the MC1 registers to read in the interrupt handler Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7730b4c7 |
|
14-Jul-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4/iw_cxgb4: work request logging feature This commit enhances the iwarp driver to optionally keep a log of rdma work request timining data for kernel mode QPs. If iw_cxgb4 module option c4iw_wr_log is set to non-zero, each work request is tracked and timing data maintained in a rolling log that is 4096 entries deep by default. Module option c4iw_wr_log_size_order allows specifing a log2 size to use instead of the default order of 12 (4096 entries). Both module options are read-only and must be passed in at module load time to set them. IE: modprobe iw_cxgb4 c4iw_wr_log=1 c4iw_wr_log_size_order=10 The timing data is viewable via the iw_cxgb4 debugfs file "wr_log". Writing anything to this file will clear all the timing data. Data tracked includes: - The host time when the work request was posted, just before ringing the doorbell. The host time when the completion was polled by the application. This is also the time the log entry is created. The delta of these two times is the amount of time took processing the work request. - The qid of the EQ used to post the work request. - The work request opcode. - The cqe wr_id field. For sq completions requests this is the swsqe index. For recv completions this is the MSN of the ingress SEND. This value can be used to match log entries from this log with firmware flowc event entries. - The sge timestamp value just before ringing the doorbell when posting, the sge timestamp value just after polling the completion, and CQE.timestamp field from the completion itself. With these three timestamps we can track the latency from post to poll, and the amount of time the completion resided in the CQ before being reaped by the application. With debug firmware, the sge timestamp is also logged by firmware in its flowc history so that we can compute the latency from posting the work request until the firmware sees it. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fc5ab020 |
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27-Jun-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Replaced the backdoor mechanism to access the HW memory with PCIe Window method Rip out a bunch of redundant PCI-E Memory Window Read/Write routines, collapse the more general purpose routines into a single routine thereby eliminating the need for a large stack frame (and extra data copying) in the outer routine, change everything to use the improved routine t4_memory_rw. Based on origninal work by Casey Leedom <leedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
0abfd152 |
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27-Jun-2014 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Use FW interface to get BAR0 value Use the firmware interface to get the BAR0 value since we really don't want to use the PCI-E Configuration Space Backdoor access which is owned by the firmware. Set up PCI-E Memory Window registers using the true values programmed into BAR registers. When the PF4 "Master Function" is exported to a Virtual Machine, the values returned by pci_resource_start() will be for the synthetic PCI-E Configuration Space and not the real addresses. But we need to program the PCI-E Memory Window address decoders with the real addresses that we're going to be using in order to have accesses through the Memory Windows work. Based on origninal work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ce100b8b |
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19-Jun-2014 |
Anish Bhatt <anish@chelsio.com> |
cxgb4 : Update copyright year on all cxgb4 files Signed-off-by: Anish Bhatt <anish@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c2b955e0 |
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13-Mar-2014 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: Updates for T5 SGE's Egress Congestion Threshold Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
68bce192 |
|
13-Mar-2014 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: Add code to dump SGE registers when hitting idma hangs Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
dcf7b6f5 |
|
18-Dec-2013 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: Add API to correctly calculate tuple fields Adds API cxgb4_select_ntuple so as to enable Upper Level Drivers to correctly calculate the tuple fields. Adds constant definitions for TP_VLAN_PRI_MAP for the Compressed Filter Tuple field widths and structures and uses them. Also, the CPL Parameters field for T5 is 40 bits so we need to prototype cxgb4_select_ntuple() to calculate and return u64 values. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7c89e555 |
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18-Dec-2013 |
Kumar Sanghvi <kumaras@chelsio.com> |
cxgb4: Include TCP as protocol when creating server filters We were creating LE Workaround Server Filters without specifying IPPROTO_TCP (6) in the filters (when F_PROTOCOL is set in TP_VLAN_PRI_MAP). This meant that UDP packets with matching IP Addresses/Ports would get caught up in the filter and be delivered to ULDs like iw_cxgb4. So, include the protocol information in the server filter properly. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
70ee3666 |
|
03-Dec-2013 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4vf: added much cleaner implementation of is_t4() Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d14807dd |
|
03-Dec-2013 |
Hariprasad Shenai <hariprasad@chelsio.com> |
cxgb4: Much cleaner implementation of is_t4()/is_t5() Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3cbdb928 |
|
13-Mar-2013 |
Vipul Pandya <vipul@chelsio.com> |
RDMA/cxgb4: Turn off db coalescing when RDMA QPs are in use. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b2decadd |
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13-Mar-2013 |
Santosh Rastapur <santosh@chelsio.com> |
cxgb4: Add register definations for T5 Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
793dad94 |
|
10-Dec-2012 |
Vipul Pandya <vipul@chelsio.com> |
RDMA/cxgb4: Fix bug for active and passive LE hash collision path Retries active opens for INUSE errors. Logs any active ofld_connect_wr error replies. Sends ofld_connect_wr on same ctrlq. It needs to go on the same control txq as regular CPL active/passive messages. Retries on active open replies with EADDRINUSE. Uses active open fw wr only if active filter region is set. Adds stat for ofld_connect_wr failures. This patch also adds debugfs file to show endpoints. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
5be78ee9 |
|
10-Dec-2012 |
Vipul Pandya <vipul@chelsio.com> |
RDMA/cxgb4: Fix LE hash collision bug for active open connection It enables establishing active open connection using fw_ofld_connection work request when cpl_act_open_rpl says TCAM full error which may be because of LE hash collision. Current support is only for IPv4 active open connections. Sets ntuple bits in active open requests. For T4 firmware greater than 1.4.10.0 ntuple bits are required to be set. Adds nocong and enable_ecn module parameter options. Signed-off-by: Vipul Pandya <vipul@chelsio.com> [ Move all FW return values to t4fw_api.h. - Roland ] Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
dca4faeb |
|
10-Dec-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: Add LE hash collision bug fix path in LLD driver It supports establishing passive open connection through firmware filter work request. Passive open connection will go through this path as now instead of listening server we create a server filter which will redirect the incoming SYN packet to the offload queue. It divides filter region into regular filters and server filter portion. It introduces new server filter region which will be exclusively used for creating server filters. This region will not overlap with regular filter region. It provides new API cxgb4_alloc_sftid in LLD for getting stid in case of LE hash collision path. This new stid will be used to open server filter in the filter region. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
ce91a923 |
|
15-Nov-2012 |
Naresh Kumar Inna <naresh@chelsio.com> |
[SCSI] cxgb4/cxgb4vf: Chelsio FCoE offload driver submission (common header updates). This patch contains updates to firmware/hardware header files shared between csiostor and cxgb4/cxgb4vf, and the resulting changes to the cxgb4/cxgb4vf source files. Signed-off-by: Naresh Kumar Inna <naresh@chelsio.com> Cc: David Miller <davem@davemloft.net> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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#
26f7cbc0 |
|
25-Sep-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: Don't attempt to upgrade T4 firmware when cxgb4 will end up as a slave This patch adds a new common code routine to upgrade an adapter's firmware. This routine handles all of the complexities of working with the the existing adapter firmware in order to quiesce the adapter and uP, etc. For an automatic upgrade it will send a HELLO command to check if cxgb4 want/can upgrade firmware, i.e. if cxgb4 is MASTER and has newer firmware that it wants to load and call the new common code routine t4_fw_upgrade. Note that it should not issue a RESET command after a successful firmware upgrade. Signed-off-by: Jay Hernandez <jay@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
13ee15d3 |
|
25-Sep-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: Add support for T4 hardwired driver configuration settings In case if user defined configuration file at /lib/firmware/cxgb4/t4-config.txt location and also factory default configuration file written to FLASH are not present then driver will use hardwired configuration settings. Signed-off-by: Jay Hernandez <jay@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
636f9d37 |
|
25-Sep-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: Add support for T4 configuration file Starting with T4 firmware version 1.3.11.0 the firmware now supports device configuration via a Firmware Configuration File. The Firmware Configuration File was primarily developed in order to centralize all of the configuration, resource allocation, etc. for Unified Wire operation where multiple Physical / Virtual Function Drivers would be using a T4 adapter simultaneously. The Firmware Configuration file can live in three locations as shown below in order of precedence. 1) User defined configuration file: /lib/firmware/cxgb4/t4-config.txt 2) Factory Default configuration file written to FLASH within the manufacturing process. 3) Hardwired driver configuration. Signed-off-by: Jay Hernandez <jay@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
52367a76 |
|
25-Sep-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4/cxgb4vf: Code cleanup to enable T4 Configuration File support This patch adds new enums and macros to enable T4 configuration file support. It also removes duplicate macro definitions. It fixes the build failure in cxgb4vf driver introduced because of old macro definition removal. It also performs SGE initialization based on T4 configuration file is provided or not. If it is provided then it uses the parameters provided in it otherwise it uses hard coded values. Signed-off-by: Jay Hernandez <jay@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
840f3000 |
|
04-Sep-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: Remove duplicate register definitions Removed duplicate definition for SGE_PF_KDOORBELL, SGE_INT_ENABLE3, PCIE_MEM_ACCESS_OFFSET registers. Moved the register field definitions around the register definition. Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Reviewed-by: Sivakumar Subramani <sivasu@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3069ee9b |
|
18-May-2012 |
Vipul Pandya <vipul@chelsio.com> |
cxgb4: DB Drop Recovery for RDMA and LLD queues recover LLD EQs for DB drop interrupts. This includes adding a new db_lock, a spin lock disabling BH too, used by the recovery thread and the ring_tx_db() paths to allow db drop recovery. Clean up initial DB avoidance code. Add read_eq_indices() - this allows the LLD to use the PCIe mw to efficiently read hw eq contexts. Add cxgb4_sync_txq_pidx() - called by iw_cxgb4 to sync up the sw/hw pidx value. Add flush_eq_cache() and cxgb4_flush_eq_cache(). This allows iw_cxgb4 to flush the sge eq context cache before beginning db drop recovery. Add module parameter, dbfoifo_int_thresh, to allow tuning the db interrupt threshold value. Add dbfifo_int_thresh to cxgb4_lld_info so iw_cxgb4 knows the threshold. Add module parameter, dbfoifo_drain_delay, to allow tuning the amount of time delay between DB FULL and EMPTY upcalls to iw_cxgb4. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
|
#
f7917c00 |
|
07-Apr-2011 |
Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
chelsio: Move the Chelsio drivers Moves the drivers for the Chelsio chipsets into drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile changes. CC: Divy Le Ray <divy@chelsio.com> CC: Dimitris Michailidis <dm@chelsio.com> CC: Casey Leedom <leedom@chelsio.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|