#
6ccf50d4 |
|
22-Sep-2023 |
Fabio Estevam <festevam@denx.de> |
net: dsa: mv88e6xxx: Avoid EEPROM timeout when EEPROM is absent Since commit 23d775f12dcd ("net: dsa: mv88e6xxx: Wait for EEPROM done before HW reset") the following error is seen on a imx8mn board with a 88E6320 switch: mv88e6085 30be0000.ethernet-1:00: Timeout waiting for EEPROM done This board does not have an EEPROM attached to the switch though. This problem is well explained by Andrew Lunn: "If there is an EEPROM, and the EEPROM contains a lot of data, it could be that when we perform a hardware reset towards the end of probe, it interrupts an I2C bus transaction, leaving the I2C bus in a bad state, and future reads of the EEPROM do not work. The work around for this was to poll the EEInt status and wait for it to go true before performing the hardware reset. However, we have discovered that for some boards which do not have an EEPROM, EEInt never indicates complete. As a result, mv88e6xxx_g1_wait_eeprom_done() spins for a second and then prints a warning. We probably need a different solution than calling mv88e6xxx_g1_wait_eeprom_done(). The datasheet for 6352 documents the EEPROM Command register: bit 15 is: EEPROM Unit Busy. This bit must be set to a one to start an EEPROM operation (see EEOp below). Only one EEPROM operation can be executing at one time so this bit must be zero before setting it to a one. When the requested EEPROM operation completes this bit will automatically be cleared to a zero. The transition of this bit from a one to a zero can be used to generate an interrupt (the EEInt in Global 1, offset 0x00). and more interesting is bit 11: Register Loader Running. This bit is set to one whenever the register loader is busy executing instructions contained in the EEPROM." Change to using mv88e6xxx_g2_eeprom_wait() to fix the timeout error when the EEPROM chip is not present. Fixes: 23d775f12dcd ("net: dsa: mv88e6xxx: Wait for EEPROM done before HW reset") Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9627c981 |
|
13-Jan-2023 |
Kurt Kanzenbach <kurt@linutronix.de> |
net: dsa: mv88e6xxx: Enable PTP receive for mv88e6390 The switch receives management traffic such as STP and LLDP. However, PTP messages are not received, only transmitted. Ideally, the switch would trap all PTP messages to the management CPU. This particular switch has a PTP block which identifies PTP messages and traps them to a dedicated port. There is a register to program this destination. This is not used at the moment. Therefore, program it to the same port as the MGMT traffic is trapped to. This allows to receive PTP messages as soon as timestamping is enabled. In addition, the datasheet mentions that this register is not valid e.g., for 6190 variants. So, add a new PTP operation which is added for the 6390 and 6290 devices. Tested simply like this on Marvell 88E6390, revision 1: |/ # ptp4l -2 -i lan4 --tx_timestamp_timeout=40 -m |[...] |ptp4l[147.450]: master offset 56 s2 freq +1262 path delay 413 |ptp4l[148.450]: master offset 22 s2 freq +1244 path delay 434 |ptp4l[149.450]: master offset 5 s2 freq +1234 path delay 446 |ptp4l[150.451]: master offset 3 s2 freq +1233 path delay 451 |ptp4l[151.451]: master offset 1 s2 freq +1232 path delay 451 |ptp4l[152.451]: master offset -3 s2 freq +1229 path delay 451 |ptp4l[153.451]: master offset 9 s2 freq +1240 path delay 451 Link: https://lore.kernel.org/r/CAFSKS=PJBpvtRJxrR4sG1hyxpnUnQpiHg4SrUNzAhkWnyt9ivg@mail.gmail.com Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
49c98c1d |
|
16-Mar-2022 |
Tobias Waldekranz <tobias@waldekranz.com> |
net: dsa: mv88e6xxx: Disentangle STU from VTU In early LinkStreet silicon (e.g. 6095/6185), the per-VLAN STP states were kept in the VTU - there was no concept of a SID. Later, the information was split into two tables, where the VTU only tracked memberships and deferred the STP state tracking to the STU via a pointer (SID). This meant that a group of VLANs could share the same STU entry. Most likely, this was done to align with MSTP (802.1Q-2018, Clause 13), which is built on this principle. While the VTU is still 4k lines on most devices, the STU is capped at 64 entries. This means that the current stategy, updating STU info whenever a VTU entry is updated, can not easily support MSTP because: - The maximum number of VIDs would also be capped at 64, as we would have to allocate one SID for every VTU entry - even if many VLANs would effectively share the same MST. - MSTP updates would be unnecessarily slow as you would have to iterate over all VLANs that share the same MST. In order to support MSTP offloading in the future, manage the STU as a separate entity from the VTU. Only add support for newer hardware with separate VTU and STU. VTU-only devices can also be supported, but essentially this requires a software implementation of an STU (fanning out state changed to all VLANs tied to the same MST). Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
bb03b280 |
|
03-Feb-2022 |
Tobias Waldekranz <tobias@waldekranz.com> |
net: dsa: mv88e6xxx: Support policy entries in the VTU A VTU entry with policy enabled is used in combination with a port's VTU policy setting to override normal switching behavior for frames assigned to the entry's VID. A typical example is to Treat all frames in a particular VLAN as control traffic, and trap them to the CPU. In which case the relevant user port's VTU policy would be set to TRAP. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
de776d0d |
|
17-Mar-2021 |
Pavana Sharma <pavana.sharma@digi.com> |
net: dsa: mv88e6xxx: add support for mv88e6393x family The Marvell 88E6393X device is a single-chip integration of a 11-port Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers and three 10-Gigabit interfaces. This patch adds functionalities specific to mv88e6393x family (88E6393X, 88E6193X and 88E6191X). The main differences between previous devices and this one are: - port 0 can be a SERDES port - all SERDESes are one-lane, eg. no XAUI nor RXAUI - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER (on 6191X only one SERDES is capable of more than 1g; USXGMII is not yet supported with this change) - Port Policy CTL register is changed to Port Policy MGMT CTL register, via which several more registers can be accessed indirectly - egress monitor port is configured differently - ingress monitor/CPU/mirror ports are configured differently and can be configured per port (ie. each port can have different ingress monitor port, for example) - port speed AltBit works differently than previously - PHY registers can be also accessed via MDIO address 0x18 and 0x19 (on previous devices they could be accessed only via Global 2 offsets 0x18 and 0x19, which means two indirections; this feature is not yet leveraged with thiis commit) Co-developed-by: Ashkan Boldaji <ashkan.boldaji@digi.com> Signed-off-by: Ashkan Boldaji <ashkan.boldaji@digi.com> Signed-off-by: Pavana Sharma <pavana.sharma@digi.com> Co-developed-by: Marek BehĂșn <kabel@kernel.org> Signed-off-by: Marek BehĂșn <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b28f3f3c |
|
25-Jan-2021 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: use mv88e6185_g1_vtu_loadpurge() for the 6250 Apart from the mask used to get the high bits of the fid, mv88e6185_g1_vtu_loadpurge() and mv88e6250_g1_vtu_loadpurge() are identical. Since the entry->fid passed in should never exceed the number of databases, we can simply use the former as-is as replacement for the latter. Suggested-by: Tobias Waldekranz <tobias@waldekranz.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
67c9ed1c |
|
25-Jan-2021 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: use mv88e6185_g1_vtu_getnext() for the 6250 mv88e6250_g1_vtu_getnext is almost identical to mv88e6185_g1_vtu_getnext, except for the 6250 only having 64 databases instead of 256. We can reduce code duplication by simply masking off the extra two garbage bits when assembling the fid from VTU op [3:0] and [11:8]. Reviewed-by: Tobias Waldekranz <tobias@waldekranz.com> Tested-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
a3dcb3e7 |
|
16-Nov-2020 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Wait for EEPROM done after HW reset When the switch is hardware reset, it reads the contents of the EEPROM. This can contain instructions for programming values into registers and to perform waits between such programming. Reading the EEPROM can take longer than the 100ms mv88e6xxx_hardware_reset() waits after deasserting the reset GPIO. So poll the EEPROM done bit to ensure it is complete. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ruslan Sushko <rus@sushko.dev> Link: https://lore.kernel.org/r/20201116164301.977661-1-rus@sushko.dev Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
ca4d632a |
|
09-Nov-2020 |
Tobias Waldekranz <tobias@waldekranz.com> |
net: dsa: mv88e6xxx: Export VTU as devlink region Export the raw VTU data and related registers in a devlink region so that it can be inspected from userspace and compared to the current bridge configuration. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20201109082927.8684-1-tobias@waldekranz.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
1baf0fac |
|
23-Jul-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
net: dsa: mv88e6xxx: Use chip-wide max frame size for MTU Some of the chips in the mv88e6xxx family don't support jumbo configuration per port. But they do have a chip-wide max frame size that can be used. Use this to approximate the behaviour of configuring a port based MTU. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d8dc2c96 |
|
04-Jan-2020 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Preserve priority when setting CPU port. The 6390 family uses an extended register to set the port connected to the CPU. The lower 5 bits indicate the port, the upper three bits are the priority of the frames as they pass through the switch, what egress queue they should use, etc. Since frames being set to the CPU are typically management frames, BPDU, IGMP, ARP, etc set the priority to 7, the reset default, and the highest. Fixes: 33641994a676 ("net: dsa: mv88e6xxx: Monitor and Management tables") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Chris Healy <cphealy@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5c74c54c |
|
07-Nov-2019 |
Iwan R Timmer <irtimmer@gmail.com> |
net: dsa: mv88e6xxx: Split monitor port configuration Separate the configuration of the egress and ingress monitor port. This allows the port mirror functionality to do ingress and egress port mirroring to separate ports. Signed-off-by: Iwan R Timmer <irtimmer@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c5f299d5 |
|
04-Nov-2019 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: global1_atu: Add helper for get next When retrieving the ATU statistics, and ATU get next has to be performed to trigger the ATU to collect the statistics. Export a helper from global1_atu to perform this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
23e8b470 |
|
24-Oct-2019 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Add devlink param for ATU hash algorithm. Some of the marvell switches have bits controlling the hash algorithm the ATU uses for MAC addresses. In some industrial settings, where all the devices are from the same manufacture, and hence use the same OUI, the default hashing algorithm is not optimal. Allow the other algorithms to be selected via devlink. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d8291a95 |
|
07-Sep-2019 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: complete ATU state definitions Marvell has different values for the state of a MAC address, depending on its multicast bit. This patch completes the definitions for these states. At the same time, use 0 which is intuitive enough and simplifies the code a bit, instead of the UC or MC unused value. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
2ad4da77 |
|
09-Aug-2019 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: remove wait and update routines Now that we have proper Wait Bit and Wait Mask routines, remove the unused mv88e6xxx_wait routine and its Global 1 and Global 2 variants. The indirect tables such as the Device Mapping Table or Priority Override Table make use of an Update bit to distinguish reading (0) from writing (1) operations. After a write operation occurs, the bit self clears right away so there's no need to wait on it. Thus keep things simple and remove the mv88e6xxx_update helper as well. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
19fb7f69 |
|
09-Aug-2019 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: introduce wait bit routine Many portions of the driver need to wait until a given bit is set or cleared. Some busses even have a specific implementation for this operation. In preparation for such variant, implement a generic Wait Bit routine that can be used by the driver core functions. This allows us to get rid of the custom implementations we may find in the driver. Note that for the EEPROM bits, BUSY and RUNNING bits are independent, thus it is more efficient to wait independently for each bit instead of waiting for their mask. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
683f2244 |
|
09-Aug-2019 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: introduce wait mask routine The current mv88e6xxx_wait routine is used to wait for a given mask to be cleared to zero. However in some cases, the driver may have to wait for a given mask to be of a certain non-zero value. Thus provide a generic wait mask routine that will be used to implement the current mv88e6xxx_wait function, and use it to wait for 88E6185 PPU states. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1f71836f |
|
04-Jun-2019 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: add support for mv88e6250 This adds support for the Marvell 88E6250. I've checked that each member in the ops-structure makes sense, and basic switchdev functionality works fine. It uses the new dual_chip option, and since its port registers start at SMI address 0x08 or 0x18 (i.e., always sw_addr + 0x08), we need to introduce a new compatible string in order for the auto-identification in mv88e6xxx_detect() to work. The chip has four per port 16-bits statistics registers, two of which correspond to the existing "sw_in_filtered" and "sw_out_filtered" (but at offsets 0x13 and 0x10 rather than 0x12 and 0x13, because why should this be easy...). Wiring up those four statistics seems to require introducing a STATS_TYPE_PORT_6250 bit or similar, which seems a tad ugly, so for now this just allows access to the STATS_TYPE_BANK0 ones. The chip does have ptp support, and the existing mv88e6352_{gpio,avb,ptp}_ops at first glance seem like they would work out-of-the-box, but for simplicity (and lack of testing) I'm eliding this. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bec8e572 |
|
04-Jun-2019 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: implement vtu_getnext and vtu_loadpurge for mv88e6250 These are almost identical to the 6185 variants, but have fewer bits for the FID. Bit 10 of the VTU_OP register (offset 0x05) is the VidPolicy bit, which one should probably preserve in mv88e6xxx_g1_vtu_op(), instead of always writing a 0. However, on the 6352 family, that bit is located at bit 12 in the VTU FID register (offset 0x02), and is always unconditionally cleared by the mv88e6xxx_g1_vtu_fid_write() function. Since nothing in the existing driver seems to know or care about that bit, it seems reasonable to not add the boilerplate to preserve it for the 6250 (which would require adding a chip-specific vtu_op function, or adding chip-quirks to the existing one). Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
df63b0d9 |
|
04-Jun-2019 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: add mv88e6250_g1_ieee_pri_map Quite a few of the existing supported chips that use mv88e6085_g1_ieee_pri_map as ->ieee_pri_map (including, incidentally, mv88e6085 itself) actually have a reset value of 0xfa50 in the G1_IEEE_PRI register. The data sheet for the mv88e6095, however, does describe a reset value of 0xfa41. So rather than changing the value in the existing callback, introduce a new variant with the 0xfa50 value. That will be used by the upcoming mv88e6250, and existing chips can be switched over one by one, preferably double-checking both the data sheet and actual hardware in each case - if anybody actually feels this is important enough to care. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
cfd10888 |
|
03-Jun-2019 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: make mv88e6xxx_g1_stats_wait static mv88e6xxx_g1_stats_wait has no users outside global1.c, so make it static. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
989f405a |
|
03-Jun-2019 |
Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
net: dsa: mv88e6xxx: fix comments and macro names in mv88e6390_g1_mgmt_rsvd2cpu The macros have an extraneous '800' (after 0180C2 there should be just six nibbles, with X representing one), while the comments have interchanged c2 and 80 and an extra :00. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
2874c5fd |
|
27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
ddca24df |
|
14-Sep-2018 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Fix ATU Miss Violation Fix a cut/paste error and a typo which results in ATU miss violations not being reported. Fixes: 0977644c5005 ("net: dsa: mv88e6xxx: Decode ATU problem interrupt") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
93e18d61 |
|
11-May-2018 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add IEEE and IP mapping ops All Marvell switch families except 88E6390 have direct registers in Global 1 for IEEE and IP priorities override mapping. The 88E6390 uses indirect tables instead. Add .ieee_pri_map and .ip_pri_map ops to distinct that and call them from a mv88e6xxx_pri_setup helper. Only non-6390 are concerned ATM. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
408d2deb |
|
11-May-2018 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: use helper for 6390 histogram The Marvell 88E6390 model has its histogram mode bits moved in the Global 1 Control 2 register. Use the previously introduced mv88e6xxx_g1_ctl2_mask helper to set them. At the same time complete the documentation of the said register. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9e5baf9b |
|
09-May-2018 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add RMU disable op The RMU mode bits moved a lot within the Global Control 2 register of the Marvell switch families. Add an .rmu_disable op to support at least 3 known alternatives. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
23c98919 |
|
09-May-2018 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: set device number All Marvell switches supported by mv88e6xxx have to set their device number in the Global Control 2 register. Extract this in a read then write function, called from the device mapping setup code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
02317e68 |
|
09-May-2018 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add a cascade port op Only the 88E6185 family has bits 15:12 Cascade Port bits in the Global Control 2 register. Hence inconsistent values are actually written in this register for other families. Add a .set_cascade_port operation to isolate the 88E6185 case, and call it from the device mapping setup function. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
62eb1162 |
|
13-Jan-2018 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Decode VTU problem interrupt When there is a problem with the VTU, an interrupt can be generated. Trap this interrupt and decode the registers to determine what the problem was, then log the error. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0977644c |
|
13-Jan-2018 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Decode ATU problem interrupt When there is a problem with the ATU, an interrupt can be generated. Trap this interrupt and decode the registers to determine what the problem was, then log the error. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
40cff8fc |
|
09-Nov-2017 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Fix stats histogram mode The statistics histogram mode was not being explicitly initialized on devices other than the 6390 family. Clearing the statistics then overwrote the default setting, setting the histogram to a reserved mode. Explicitly set the histogram mode for all devices. Change the statistics clear into a read/modify/write, and since it is now more complex, move it into global1.c. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ccba8f3a |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Prio and Tag macros Prefix and document the remaining Global IP and IEEE Priority and Core Tag Type registers and give them a clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
57d1ef38 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Stats macros Prefix and document the Global Stats Operation and Counter registers and give them a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
101515c8 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Monitor Control macros Prefix and document the Global Monitor Control Register macros (which became the Global Monitor & MGMT Control Register with 88E6390) and give a clear 16-bit registers representation. Use __bf_shf to get the shift value at compile time instead of adding new defined macros for it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d77f4321 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Control macros Prefix and document the Global Control and Control 2 registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7ec60d6e |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global VTU macros Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
27c0e600 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global ATU macros Prefix and document the Global ATU Registers macros and give clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4b0c4817 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Switch MAC macros Prefix and document the Global Switch MAC Address Register macros and give clear 16-bit register representation. At the same time, move mv88e6xxx_g1_set_switch_mac in global1.c, where it belongs. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
82466921 |
|
14-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: prefix Global Status macros Prefix and document the Global Status Register macros and give clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e097097b |
|
02-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move the Global 1 macros Move the GLOBAL_* macros where they belong, in the related global1.h header. Include it in global2.c which uses GLOBAL_STATUS_IRQ_DEVICE. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4d5f2ba7 |
|
02-Jun-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: rename chip header The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. At the same time, ensure that relative header inclusions are separated by a newline and sorted alphabetically. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
931d1822 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add VTU support for 88E6390 The 6390 family of chips use only 2 of the 3 VTU Data registers to pack the MemberTag and PortState VLAN data. This means that they must be written or read before or after each VTU/STU operations. Implement this variant to add support for VTU with such chips. These chips have a 13th bit for the VID thus set their max_vid to 8191. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bf7d71c0 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: make VTU helpers static Now that we have chip operations for VTU accesses, mark all helpers from global1_vtu.c as static. Only the various implementations of the GetNext, LoadPurge and Flush operations need to be exposed. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0ad5daf6 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add VTU Load/Purge operation Add a new vtu_loadpurge operation to the chip info structure to differ the various implementations of the VTU accesses. Now that the STU handling is abstracted behind VTU operations, kill the obsolete MV88E6XXX_FLAG_STU flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f1394b78 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add VTU GetNext operation Add a new vtu_getnext operation to the chip info structure to differ the various implementations of the VTU accesses. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ef6fcea3 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: get STU entry on VTU GetNext Now that the code reads both VTU and STU data on VTU GetNext operation, fetch the STU entry data of a VTU entry at the same time. The STU data bits are masked with the VTU data bits and they are now all read at the same time a VTU GetNext operation is issued. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
66a8e1f9 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move STU GetNext operation Extract the generic portion of code to issue an STU GetNext operation, which will be used in other implementations. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c499a64f |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU Data accessors The code to access the VTU Data registers currently only supports the 88E6185 family and alike: 2-bit membership adjacent to 2-bit port state. Even though the 88E6352 family introduced an indirect table to program the VLAN Spanning Tree states, the usage of the VTU Data registers remains the same regardless the VTU or STU operation. Now that the mv88e6xxx_vtu_entry structure contains both port membership and states data, factorize the code to access them in global1_vtu.c. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f169e5ee |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move generic VTU GetNext Even though every switch model has a different way to access the VTU Data bits, the base implementation of the VTU GetNext operation remains the same: wait, write the first VID to iterate from, start the operation, and read the next VID. Move this generic implementation into global1_vtu.c and abstract the handling of the start VID (similarly to the ATU GetNext implementation), before introducing a new chip operation for specific chips. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3afb4bde |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU VID accessors Add helpers to access the VTU VID register in the global1_vtu.c file. At the same time, move mv88e6xxx_g1_vtu_vid_write at the beginning of _mv88e6xxx_vtu_loadpurge, which adds no functional changes but makes future patches simpler. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d2ca1ea1 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU SID accessors Add helpers to access the VTU SID register in the global1_vtu.c file. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8ee51f6b |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU FID accessors Add helpers to access the VTU FID register in the global1_vtu.c file. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b486d7c9 |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU flush Move the VTU flush operation to global1_vtu.c and call it from a mv88e6xxx_vtu_setup helper, similarly to the ATU and PVT setup. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
332aa5cc |
|
01-May-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move VTU Operation accessors Move the helper functions to access the Global 1 VTU Operation register to a new global1_vtu.c file, and get rid of the old underscore prefix naming convention. This file will be extended will all VTU/STU related code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4333d619 |
|
28-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: fix copyright holder I do not hold the copyright of the DSA core and drivers source files, since these changes have been written as an initiative of my day job. Fix this. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e606ca36 |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: rework ATU Remove Add a fresh documented implementation of the ATU Move operation, and use it to replace the current ATU Remove operation. Note that not all Marvell switch chip support the ATU Move operation. For those supporting it, the number of bits used to mask the destination port may vary. 6352 and such use 4-bit, while 6390 use 5-bit. Thus add a new atu_move_port_mask member in the info structure to describe the presence and variant of ATU Move operation. Note that the ATU Move operation is not documented in the 6185 datasheet but the chip does support the operation. All remaining _mv88e6xxx_atu_* functions are now unused as well as the MV88E6XXX_FLAG_G1_ATU_FID flag, thus remove them. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
daefc943 |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: rework ATU Flush Add a fresh documented implementation of the ATU Flush/Move operation. Use it to replace the current ATU Flush operation. _mv88e6xxx_atu_flush_move is still used by the Move operation so keep it until the Move operation is refactored in a next commit. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
dabc1a96 |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: rework ATU GetNext Add and use a fresh documented implementation of the ATU GetNext. Since it is not necessary to write the MAC address to iterate from, only do it once directly in the ATU GetNext operation, if the provided ATU entry structure is not valid. This makes the user code simpler. Also, there is no need to loop when getting a single ATU entry. So remove the mv88e6xxx_atu_get helper and add a simpler snippet in mv88e6xxx_port_db_load_purge to lookup a given MAC address. The _mv88e6xxx_atu_mac_{read,write} are not used anymore thus remove them. _mv88e6xxx_atu_data_{read,write} are still used so keep them. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9c13c026 |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: rework ATU Load/Purge All Marvell switch chips have an ATU accessed using the same Global (1) register layout. Only the handling of the FID differs as more bits were necessary to support more and more databases. Add and use a fresh documented implementation of the ATU Load/Purge. The static mv88e6xxx_g1_atu_{fid_write,op_wait,op,data_write,mac_write} functions won't need to be exposed in the end so for the moment keep their counterparts _mv88e6xxx_atu_{wait,cmd,data_write,mac_write} as is, since they are still used by other ATU operations. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c3a7d4ad |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: enable ATU Learn2All The ATU Learn2All feature allows newly learnt addresses to be spanned on ports marked as "Message Port", currently all DSA ports. This commit enables this feature which is necessary and quite convenient for multi-chip switch fabrics. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
720c6343 |
|
11-Mar-2017 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: move ATU ageing time setter Move the ATU ageing time setter code in a new global1_atu.c file, which will be extended in future patches to contains all consequent Global (1) ATU support code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a199d8b6 |
|
05-Dec-2016 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add PPU operations Some Marvell chips can enable/disable the PPU on demand. This is needed to access the PHY registers when there is no indirection mechanism. Add two new ppu_enable and ppu_disable ops to describe this and finally get rid of the MV88E6XXX_FLAG_PPU* flags. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
17e708ba |
|
05-Dec-2016 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add a soft reset operation Marvell chips have different way to issue a software reset. Old chips (such as 88E6060) have a reset bit in an ATU control register. Newer chips moved this bit in a Global control register. Chips with controllable PPU should reset the PPU when resetting the switch. Add a new reset operation to implement these differences and introduce a mv88e6xxx_software_reset() helper to wrap it conveniently. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6e55f698 |
|
02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Reserved Management frames to CPU Older devices have a couple of registers in global2. The mv88e6390 family has a single register in global1 behind which hides similar configuration. Implement and op for this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
33641994 |
|
02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Monitor and Management tables The mv88e6390 changes the monitor control register into the Monitor and Management control, which is an indirection register to various registers. Add ops to set the CPU port and the ingress/egress port for both register layouts, to global1 Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7f9ef3af |
|
21-Nov-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Move g1 stats code in global1.[ch] Move the stats functions which access global 1 registers into global1.c. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
de227387 |
|
21-Nov-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Add mv88e6390 statistics unit init The statistics unit on the mv88e6390 needs the histogram mode to be configured in a different register compared to other devices. Add an ops to do this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> v2: Rename to mv88e6390_g1_stats_set_histogram Move into global1.c Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
79523473 |
|
21-Nov-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Add mv88e6390 stats snapshot operation The MV88E6390 has a control register for what the histogram statistics actually contain. This means the stat_snapshot method should not set this information. So implement the 6390 stats_snapshot function without these bits. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a605a0fe |
|
21-Nov-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Abstract stats_snapshot into ops structure Taking a stats snapshot differs between same families. Abstract this into an ops member. At the same time, move the code into global1.[ch], since the registers are in the global1 range. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a935c052 |
|
28-Sep-2016 |
Vivien Didelot <vivien.didelot@gmail.com> |
net: dsa: mv88e6xxx: add global1 helpers The Global (1) internal SMI device is an extended set of registers containing ATU, PPU, VTU, STU, etc. It is present on every switches, usually at SMI address 0x1B. But old models such as 88E6060 access it at address 0xF, thus using REG_GLOBAL is erroneous. Add a global1_addr info member used by mv88e6xxx_g1_{read,write} and mv88e6xxx_g1_wait helpers in a new global1.c file. This patch finally removes _mv88e6xxx_reg_{read,write}, in favor on the appropriate helpers. No functional changes here. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|