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8e52f54c |
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07-Sep-2023 |
Michael Walle <mwalle@kernel.org> |
mtd: spi-nor: xilinx: use new macros in S3AN_INFO() There won't be any new entries, nor are the entries that much different and the very odd page and sector sizes make the new format hard to read. Therefore, convert the old S3AN_INFO() macro. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-29-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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e255a791 |
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07-Sep-2023 |
Michael Walle <mwalle@kernel.org> |
mtd: spi-nor: default .n_banks to 1 If .n_banks is not set in the flash_info database, the default value should be 1. This way, we don't have to always set the .n_banks parameter in flash_info. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-8-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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0554effe |
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07-Sep-2023 |
Michael Walle <mwalle@kernel.org> |
mtd: spi-nor: convert .n_sectors to .size .n_sectors is rarely used. In fact it is only used in swp.c and to calculate the flash size in the core. The use in swp.c might be converted to use the (largest) flash erase size. For now, we just locally calculate the sector size. Simplify the flash_info database and set the size of the flash directly. This also let us use the SZ_x macros. Verified that there's no flash that specifies BP and sector size of zero to make sure we avoid a division by zero in spi_nor_get_min_prot_length_sr(). We'll protect from a possible division by zero in a further patch by introducing a default value for sector_size. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-5-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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afbfb8c5 |
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07-Sep-2023 |
Michael Walle <mwalle@kernel.org> |
mtd: spi-nor: xilinx: remove addr_nbytes from S3AN_INFO() The default value of addr_nbytes is already 3. Drop it. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-4-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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74b7ad76 |
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07-Sep-2023 |
Michael Walle <mwalle@kernel.org> |
mtd: spi-nor: xilinx: use SPI_NOR_ID() in S3AN_INFO() In commit 59273180299a ("mtd: spi-nor: Create macros to define chip IDs and geometries") SPI_NOR_ID() were introduced, but it did only update the INFO() macro in core.h. Also use it in S3AN_INFO(). Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-3-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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d534fd97 |
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26-Jul-2023 |
Takahiro Kuwano <Takahiro.Kuwano@infineon.com> |
mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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9d6c5d64 |
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28-Mar-2023 |
Miquel Raynal <miquel.raynal@bootlin.com> |
mtd: spi-nor: Introduce the concept of bank SPI NOR chips are made of pages, which gathered in small groups make (erase) sectors. Sectors, gathered together, make banks inside the chip. Until now, there was only one bank per device supported, but we are about to introduce support for new chips featuring several banks (up to 4 so far) where different operations may happen in parallel. Let's allow describing these additional bank parameters, and let's do this independently of any other value (like the number of sectors) with an absolute value. By default we consider that all chips have a single bank. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20230328154105.448540-2-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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c452d498 |
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24-Jul-2022 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: s/addr_width/addr_nbytes Address width was an unfortunate name, as it means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR framework. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com
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c0abb861 |
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20-Apr-2022 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: Introduce templates for SPI NOR operations Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220420103427.47867-10-tudor.ambarus@microchip.com
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56b852e8 |
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23-Feb-2022 |
Michael Walle <michael@walle.cc> |
mtd: spi-nor: xilinx: correct the debug message XRDSR is a combination of xilinx and the RDSR opcode, but the register is just the status register. Correct the debug message. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-24-michael@walle.cc
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8b7a2e00d |
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23-Feb-2022 |
Michael Walle <michael@walle.cc> |
mtd: spi-nor: xilinx: rename vendor specific functions and defines Drop the generic spi_nor prefix for all the xilinx functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-23-michael@walle.cc
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8b4195cd |
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23-Feb-2022 |
Michael Walle <michael@walle.cc> |
mtd: spi-nor: move all xilinx specifics into xilinx.c Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
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45acce20 |
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23-Feb-2022 |
Michael Walle <michael@walle.cc> |
mtd: spi-nor: xilinx: unify function names To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-16-michael@walle.cc
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eb726c32 |
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07-Dec-2021 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: core: Don't use mtd_info in the NOR's probe sequence of calls Use NOR parameters in the probe's sequence of calls, thus nor->params->size instead of nor->mtd.size and let the mtd_info fields be used by the mtd calls (mtd->_erase, mtd->_read, mtd->_write). mtd_info fields should not be used during probe because we haven't registered mtd yet. It's safe to drop xilinx's setting of nor->mtd.size, now that we use nor->params->size in spi_nor_set_addr_width(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-3-tudor.ambarus@microchip.com
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f656b419 |
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07-Dec-2021 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: Fix mtd size for s3an flashes As it was before the blamed commit, s3an_nor_scan() was called after mtd size was set with params->size, and it overwrote the mtd size value with '8 * nor->page_size * nor->info->n_sectors' when XSR_PAGESIZE was set. With the introduction of s3an_post_sfdp_fixups(), we missed to update the mtd size for the s3an flashes. Fix the mtd size by updating both nor->params->size, (which will update the mtd_info size later on) and nor->mtd.size (which is used in spi_nor_set_addr_width()). Fixes: 641edddb4f43 ("mtd: spi-nor: Add s3an_post_sfdp_fixups()") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-2-tudor.ambarus@microchip.com
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3fdad69e |
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29-Oct-2021 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: xilinx: Use manufacturer late_init() to set setup method post_sfdp was misleading in this case, as SFDP is not supported by xilinx. Plus, there's no fixup here, just setting the correct setup method, as required by xilinx parts. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211029172633.886453-10-tudor.ambarus@microchip.com
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5854d4a6 |
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29-Oct-2021 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: Get rid of nor->page_size nor->page_size duplicated what nor->params->page_size indicates for no good reason. page_size is a flash parameter of fixed value and it is better suited to be found in nor->params->page_size. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20211029172633.886453-5-tudor.ambarus@microchip.com
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829ec640 |
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13-Mar-2020 |
Tudor Ambarus <tudor.ambarus@microchip.com> |
mtd: spi-nor: Trim what is exposed in spi-nor.h The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. struct spi_nor_flash_parameter is filled at run-time with info gathered from flash_info, manufacturer and sfdp data. struct spi_nor_flash_parameter should be opaque to the SPI NOR controller drivers, make sure it is. spi_nor_option_flags, spi_nor_read_command, spi_nor_pp_command, spi_nor_read_command_index and spi_nor_pp_command_index are defined for the core use, make sure they are opaque to the SPI NOR controller drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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2d47cac1 |
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13-Mar-2020 |
Boris Brezillon <bbrezillon@kernel.org> |
mtd: spi-nor: Move Xilinx bits out of core.c Create a SPI NOR manufacturer driver for Xilinx chips, and move the Xilinx definitions outside of core.c. While at it, remove the SPI_S3AN flag which is now useless. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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