#
805946a2 |
|
27-Jul-2023 |
Yangtao Li <frank.li@vivo.com> |
mmc: sunxi: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230727070051.17778-1-frank.li@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c2df53c58 |
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17-Jun-2023 |
Sergey Shtylyov <s.shtylyov@omp.ru> |
mmc: sunxi: fix deferred probing The driver overrides the error codes and IRQ0 returned by platform_get_irq() to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs, so we now can safely ignore it... Fixes: 2408a08583d2 ("mmc: sunxi-mmc: Handle return value of platform_get_irq") Cc: stable@vger.kernel.org # v5.19+ Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230617203622.6812-12-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
85094197 |
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09-Aug-2022 |
Samuel Holland <samuel@sholland.org> |
mmc: sunxi-mmc: Fix clock refcount imbalance during unbind If the controller is suspended by runtime PM, the clock is already disabled, so do not try to disable it again during removal. Use pm_runtime_disable() to flush any pending runtime PM transitions. Fixes: 9a8e1e8cc2c0 ("mmc: sunxi: Add runtime_pm support") Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220810022509.43743-1-samuel@sholland.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
32f18e59 |
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08-Apr-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: improve API to make clear hw_reset callback is for cards To make it unambiguous that the hw_reset callback is for cards and not for controllers, we add 'card' to the callback name and convert all users in one go. We keep the argument as mmc_host, though, because the callback is used very early when mmc_card is not yet populated. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220408080045.6497-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e9f3fb52 |
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24-Apr-2022 |
Samuel Holland <samuel@sholland.org> |
mmc: sunxi-mmc: Fix DMA descriptors allocated above 32 bits Newer variants of the MMC controller support a 34-bit physical address space by using word addresses instead of byte addresses. However, the code truncates the DMA descriptor address to 32 bits before applying the shift. This breaks DMA for descriptors allocated above the 32-bit limit. Fixes: 3536b82e5853 ("mmc: sunxi: add support for A100 mmc controller") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220424231751.32053-1-samuel@sholland.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
75a2f412 |
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02-Feb-2022 |
Samuel Holland <samuel@sholland.org> |
mmc: sunxi-mmc: Add D1 MMC variant D1's MMC controllers are unique in that they have the DMA address shift (like A100) with a 13-bit descriptor size field (like sun4i). Add the compatible and parameters for this new variant. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220203015112.12008-2-samuel@sholland.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3882917d |
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12-Jan-2021 |
Samuel Holland <samuel@sholland.org> |
mmc: sunxi-mmc: Ensure host is suspended during system sleep If the device suspend process begins before the mmc host's autosuspend timeout, the host will continue running during system sleep. Avoid this by forcing runtime suspend during a global suspend transition. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20210113052421.36553-1-samuel@sholland.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3536b82e |
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10-Dec-2020 |
Yangtao Li <frank@allwinnertech.com> |
mmc: sunxi: add support for A100 mmc controller This patch adds support for A100 MMC controller, which use word address for internal dma. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20201211011934.6171-10-andre.przywara@arm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b733775f |
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26-Oct-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
mmc: sunxi: drop of_match_ptr from of_device_id table The driver can match only via DT table so it should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it is not relevant for sunxi). This fixes compile warning: drivers/mmc/host/sunxi-mmc.c:1181:34: warning: ‘sunxi_mmc_of_match’ defined but not used [-Wunused-const-variable=] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20201026153810.89512-3-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
21b2cec6 |
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03-Sep-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.4 This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # SH_MMCIF Tested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200903162412.1.Id501e96fa63224f77bb86b2135a5e8324ffb9c43@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1be64c79 |
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08-May-2020 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: host: Drop redundant MMC_CAP_ERASE The MMC_CAP_ERASE bit is no longer used by the mmc core as erase, discard and trim operations are now always supported. Therefore, drop the bit and move all mmc hosts away from using it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rui Miguel Silva <rmfrfs@gmail.com> Link: https://lore.kernel.org/r/20200508112902.23575-1-ulf.hansson@linaro.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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#
9cbe0fc8 |
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16-Apr-2020 |
Marek Vasut <marex@denx.de> |
mmc: host: Prepare host drivers for mmc_regulator_set_vqmmc() returning > 0 Patch all drivers which use mmc_regulator_set_vqmmc() and prepare them for the fact that mmc_regulator_set_vqmmc() can return a value > 0, which would happen if the signal voltage switch did NOT happen, because the voltage was already set correctly. Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20200416163649.336967-1-marex@denx.de [Ulf: Re-worked/simplified the code a bit] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c5c52c37 |
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15-Dec-2019 |
Yangtao Li <tiny.windzz@gmail.com> |
mmc: sunxi-mmc: convert to devm_platform_ioremap_resource Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20191215175120.3290-1-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
bed12fb0 |
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11-Feb-2019 |
Linus Walleij <linus.walleij@linaro.org> |
mmc: sunxi-mmc: Drop unused includes The Sunxi MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Andre Przywara <andre.przywara@arm.com> Cc: cenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d6f11e7d |
|
05-Feb-2019 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Filter out unsupported modes declared in the device tree The MMC device tree bindings include properties used to signal various signalling speed modes. Until now the sunxi driver was accepting them without any further filtering, while the sunxi device trees were not actually using them. Since some of the H5 boards can not run at higher speed modes stably, we are resorting to declaring the higher speed modes per-board. Regardless, having boards declare modes and blindly following them, even without proper support in the driver, is generally a bad thing. Filter out all unsupported modes from the capabilities mask after the device tree properties have been parsed. Cc: <stable@vger.kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d49d92ac |
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05-Feb-2019 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Some H5 boards seem to not have proper trace lengths for eMMC to be able to use the default setting for the delay chains under HS-DDR mode. These include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre Computer ALL-H3-CC-H5 works just fine. For the H5 (at least for now), default to not enabling HS-DDR modes in the driver, and expect the device tree to signal HS-DDR capability on boards that work. Reported-by: Chris Blake <chrisrblake93@gmail.com> Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller") Cc: <stable@vger.kernel.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
07bafc1e |
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06-Sep-2018 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Use new timing mode for A64 eMMC controller The eMMC controller is also a new timing mode controller, but it doesn't have the timing mode switch. It does however have signal delay and calibration controls, typical of Allwinner MMC controllers that support the new timing mode. Enable the new timing mode setting for the A64 eMMC controller. This also enables MMC HS-DDR modes, which gives higher throughput for eMMC chips that support it, and can deliver such throughput. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1ff9cabd |
|
06-Sep-2018 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Clarify new timing mode usage and implementation Newer sunxi mmc controller variants support what they call the "new timing mode". Support for this was implemented in two ways, according to the hardware that was seen at the time. The first type retained the old timing mode, and both the clock and mmc controllers had switches to select which mode was used. Both switches had to be set to the same setting. This variant was denoted with the .has_timings_switch field in the sunxi_mmc_cfg structure. This hardware is only seen on the A83T. The second type did away with the old timing mode. The clock controller no longer had the mode selection or clock delay setting bits. In some cases the mmc controller retained its mode selection bit, but this always needed to be set to the new mode, or instabilities would occur. In a few cases, such as the A64 and H6 eMMC controller, the mode selection bit is gone, but the controller still behaves like the new timing mode, requiring the module clock to be double the card clock in DDR transfer modes. This variant is denoted with the .needs_new_timings field. This patch adds more comments explaining the two fields, as well as the possibly nonexistent mode switch in the mmc controller. The .has_timings_switch is renamed to .ccu_has_timings_switch to clarify its meaning. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1389690b |
|
23-Jul-2018 |
Andre Przywara <andre.przywara@arm.com> |
mmc: sunxi: remove output of virtual base address Recent Linux versions refuse to print actual virtual kernel addresses, to not give a hint about the location of the kernel in a randomized virtual address space. This affects the output of the sunxi MMC controller driver, which now produces the rather uninformative line: [ 1.482660] sunxi-mmc 1c0f000.mmc: base:0x(____ptrval____) irq:8 Since the virtual base address is not really interesting in the first place, let's just drop this value. The same applies to Linux' notion of the interrupt number, which is independent from the GIC SPI number. We have the physical address as part of the DT node name, which is way more useful for debugging purposes. To keep a success message in the driver, we make this purpose explicit with the word "initialized", plus print some information that is not too obvious and that we learned while probing the device: the maximum request size and whether it uses the new timing mode. So the output turns into: [ 1.750626] sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB, uses new timings mode [ 1.786699] sunxi-mmc 1c11000.mmc: initialized, max. request size: 2048 KB Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
88023d43 |
|
22-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
mmc: sunxi: allow 3.3V DDR when DDR is available Some Allwinner boards feature an on-board eMMC with fixed 3.3V voltage (e.g. Banana Pi M2+), and in this case both the eMMC and the SoC are capable of doing 3.3V DDR transmission. Add capability of 3.3V DDR when DDR is available (extra clock or new timing). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b8ba3578 |
|
04-Jul-2018 |
Stefan Mavrodiev <stefan@olimex.com> |
mmc: sunxi: Disable irq during pm_suspend When mmc host controller enters suspend state, the clocks are disabled, but irqs are not. For some reason the irqchip emits false interrupts, which causes system lock loop. Debug log is: ... sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded 51200000 sunxi-mmc 1c11000.mmc: enabling the clock sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 6(80000146) arg 3210101 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 AGND3R 14.6 GiB mmcblk1boot0: mmc1:0001 AGND3R partition 1 4.00 MiB mmcblk1boot1: mmc1:0001 AGND3R partition 2 4.00 MiB sunxi-mmc 1c11000.mmc: cmd 18(80003352) arg 0 ie 0x0000fbc2 len 409 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00004000 idi 00000002 mmcblk1: p1 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 and so on... This issue apears on eMMC cards, routed on MMC2 slot. The patch is tested with A20-OLinuXino-MICRO/LIME/LIME2 boards. Fixes: 9a8e1e8cc2c0 ("mmc: sunxi: Add runtime_pm support") Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
af6b8ff4 |
|
30-May-2018 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: sunxi: Use ifdef rather than __maybe_unused To be consistent with code in other mmc host drivers, convert to check the correct PM config #ifdef in favor of using __maybe_unused. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
45ee5046 |
|
25-May-2018 |
Arnd Bergmann <arnd@arndb.de> |
mmc: sunxi: mark PM functions as __maybe_unused The newly added runtime-pm functions cause a harmless warning when CONFIG_PM is disabled: drivers/mmc/host/sunxi-mmc.c:1452:12: error: 'sunxi_mmc_runtime_suspend' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_suspend(struct device *dev) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mmc/host/sunxi-mmc.c:1435:12: error: 'sunxi_mmc_runtime_resume' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_resume(struct device *dev) This marks them as __maybe_unused to shut up the warning. Fixes: 9a8e1e8cc2c0 ("mmc: sunxi: Add runtime_pm support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
eef797ac |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Drop the init / reset of the controller from set_ios Our set_ios hook is, when the card is power up or down, either doing a full init or put our controller back into a reset mode. Since we're also doing that in our runtime_pm hooks, and at possibly much more often, we can drop it from the set_ios, and either rely on our runtime_pm hooks or our probe to do it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
9a8e1e8c |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Add runtime_pm support So far, even if our card was not in use, we didn't shut down our MMC controller, which meant that it was still active and clocking the bus. While this obviously means that we could save some power there, it also creates issues when it comes to EMC control since we'll have a perfect peak at the card clock rate. Let's implement runtime_pm with autosuspend so that we will shut down the controller when it's not been in use for quite some time. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e27e1f3d |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Move the card power configuration to a function In order to improve readibility and reusability, let's move the card setup to a small function called by our .set_ios hook. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ad04d955 |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Move clock configuration to a function In order to improve readibility and reusability, let's move the clock setup to a small function called by our .set_ios hook. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3f6c808e |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Move bus width configuration to a function In order to improve readibility and reusability, let's move the bus width setup to a small function called by our .set_ios hook. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
0fc4c61f |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Change sunxi_mmc_init_host argument type All the other functions in the driver take a struct sunxi_mmc_host pointer. Let's make it consistent. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
743b819e |
|
16-Apr-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Reorder the headers Our headers sort algorithm has had pretty chaotic results. Let's fix that. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
cb1214d2 |
|
08-Mar-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Set our device drvdata earlier As soon as the pm_runtime_enable hook is called, our runtime_suspend and runtime_resume hooks can be called as well. However, we only set the device drvdata that we will use after we have registered into the MMC core. Move that earlier so that we don't have a race that could lead to a crash. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d8181941 |
|
08-Mar-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Move the reset deassertion before enabling the clocks As per Allwinner guidelines, the reset line should be deasserted before turning the clocks on. Implement it in our driver as well. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
774c0103 |
|
08-Mar-2018 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Move resources management to separate functions We've had all our resources management, and especially the clocks and reset sequence, done directly as part of the probe. As we want to implement runtime_pm, we'll obviously want to have that moved outside of the probe so that we can call do it in our runtime suspend and resume hooks without too much duplication. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2408a085 |
|
18-Nov-2017 |
Arvind Yadav <arvind.yadav.cs@gmail.com> |
mmc: sunxi-mmc: Handle return value of platform_get_irq platform_get_irq() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1907e386 |
|
27-Nov-2017 |
Adam Borowski <kilobyte@angband.pl> |
mmc: sunxi: fix mojibake in module metadata It had an U+FFFD: not a corrupted character but a literal well-formed replacement marker. Signed-off-by: Adam Borowski <kilobyte@angband.pl> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
aaab3c46 |
|
08-Oct-2017 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: sunxi: drop superfluous error message This error message can go because a) currently nothing else than EPROBE_DEFER is returned and b) if this is going to change a much more detailed error message should come from mmc_regulator_get_supply() anyhow. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c34eda69 |
|
25-Aug-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Reset the device at probe time We might be into some troubles if the bootloader misconfigured the MMC controller. We currently only de-assert the reset line at probe time, which means that if the device was already out of reset, we're going to keep whatever state was set already. Switch to a reset instead of the deassert to have a device in a pristine state when we start operating. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
082bb85f |
|
09-Aug-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Fix clock rate passed to sunxi_mmc_clk_set_phase sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed to it. When the internal divider code was reworked in change ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"), this requirement was missed, and the module clock rate was passed in instead. This broke 8 bit DDR MMC on old controllers, as the module clock rate is double the card clock rate, for which we have no valid delay settings. Fix this by applying the internal divider to the clock rate right after we configure it in hardware. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
b939e0b7 |
|
08-Aug-2017 |
Icenowy Zheng <icenowy@aosc.io> |
mmc: sunxi: fix support for new timings mode only SoCs The A83T MMC support code introduces the timings mode switch, however such a switch doesn't exist on new SoCs with only new timings mode. Only execute the switch if the SoC really have the timings mode switch, to fix the regression shown on new timings mode only SoCs (A64, H5, etc). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
a6461134 |
|
08-Aug-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Fix NULL pointer reference on clk_delays Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was replaced in change "mmc: sunxi: Support controllers that can use both old and new timings". This patch adds back the check for clk_delays, and also adds comments for both checks in sunxi_mmc_clk_set_phase(). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ac98caef |
|
24-Jul-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Add support for A83T eMMC (MMC2) The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly different. It supports a wider 8-bit bus, has a dedicated controllable reset pin for eMMC, and a "new timing mode" which is supposed to deliver better signals and thus better performance. Add a compatible for this one to use the new timing mode not found in the other controllers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c903a2ae |
|
24-Jul-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode The MMC controller can support DDR52 transfers under the new timing mode. According to the BSP kernel, the module clock has to be double the card clock, regardless of the bus width. The default timings in the hardware can be used. This also reworks the code setting the internal divider, getting rid of a extra conditional. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
ff39e7f7 |
|
24-Jul-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support controllers that can use both old and new timings On the SoCs that introduced the new timing mode for MMC controllers, both the old (where the clock delays are set in the CCU) and new (where the clock delays are set in the MMC controller) timing modes are available, and we have to support them both. However there are two bits that control which mode is active. One is in the CCU, the other is in the MMC controller. The settings on both sides must be the same, or nothing will work. The sunxi-ng clock driver provides an API to query and set the active timing mode. At probe time, we try to set the active mode to the "new timing mode". If it succeeds, we can then use the MMC controller in the new mode. If not, we fall back to the old mode. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
1f8029c3 |
|
28-Jul-2017 |
Julia Lawall <Julia.Lawall@lip6.fr> |
mmc: sunxi: constify mmc_host_ops structures The mmc_host_ops structure is only stored in the ops field of an mmc_host structure, which is declared as const. Thus the mmc_host_ops structure itself can be const. Done with the help of Coccinelle. // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct mmc_host_ops i@p = { ... }; @ok1@ struct mmc_host *mmc; identifier r.i; position p; @@ mmc->ops = &i@p @bad@ position p != {r.p,ok1.p}; identifier r.i; struct mmc_host_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct mmc_host_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
5e40ddac |
|
19-Jul-2017 |
Philipp Zabel <p.zabel@pengutronix.de> |
mmc: sunxi: explicitly request exclusive reset control Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
26cb2be4 |
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14-Jul-2017 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Keep default timing phase settings for new timing mode The register for the "new timing mode" also has bit fields for setting output and sample timing phases. According to comments in Allwinner's BSP kernel, the default values are good enough. Keep the default values already in the hardware when setting new timing mode, instead of overwriting the whole register. Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC controllers") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
feeef096 |
|
26-Mar-2017 |
Heiner Kallweit <hkallweit1@gmail.com> |
mmc: use new core function mmc_get_dma_dir Use new core function mmc_get_dma_dir(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
bd675698 |
|
16-Mar-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
mmc: sunxi: change controller error info to debug level The controller's errors are usually normal (for example, for MMC or SDIO cards, some errors are expected to happen; and for boards without a dedicated card detect pin the error info will even flood console and hide other normal messages) and hard to understand. Change their print level to debug, thus it won't be shown to generic users. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
43c15e96 |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Add more debug informations Add a bit more debug messages that can be helpful when debugging the clock setup. Also fill the actual_clock field in struct mmc_host to report properly the current frequency in debugfs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
4fb3ce07 |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Add EMMC (MMC2) controller compatible The MMC2 controller on the A64 is kind of a special beast. While the general controller design is the same than the other MMC controllers in the SoC, it also has a bunch of features and changes that prevent it to be driven in the same way. It has for example a different bus width limit, a different maximum frequency, and, for some reason, the maximum buffer size of a DMA descriptor. Add a new compatible specifically for this controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
16e821e3 |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Mask DATA0 when updating the clock The A64 MMC controllers need DATA0 to be masked while updating the clock, otherwise any subsequent command will result in a timeout. It's not really clear at this point what DATA0 is exactly, but this behaviour is present in Allwinner's tree, and has been suggested by Allwinner engineers as fixes for the timeout. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
9a37e53e |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Enable the new timings for the A64 MMC controllers The A64 MMC controllers need to set a "new timings" bit when a new rate is set. The actual meaning of that bit is not clear yet, but not setting it leads to some corner-case issues, like the CMD53 failing, which is used to implement SDIO packet aggregation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
860fdf89 |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Always set signal delay to 0 for A64 Experience have shown that the using the autocalibration could severely degrade the performances of the MMC bus. Allwinner is using in its BSP a delay set to 0 for all the modes but HS400. Remove the calibration code for now, and add comments to document our findings. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
9479074e |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Gate the clock when rate is 0 The MMC core assumes that the code will gate the clock when the bus frequency is set to 0, which we've been ignoring so far. Handle that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
39cc281f |
|
27-Jan-2017 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Fix clock frequency change sequence The SD specification documents that the clock frequency should only be changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence). The current code first modifies the parent clock, gates it and then modifies the internal divider. This means that since the parent clock rate might be changed, the bus clock might be changed as well before it is gated, which breaks the specification. Move the gating before the parent rate modification. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
424feb59 |
|
19-Oct-2016 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Prevent against null dereference for vmmc VMMC is an optional regulator, which means that mmc_regulator_get_supply will only return an error in case of a deferred probe, but not when the regulator is not set in the DT. However, the sunxi driver assumes that VMMC is always there, and doesn't check the value of the regulator pointer before using it, which obviously leads to a (close to) null pointer dereference. Add proper checks to prevent that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
e1b8dfd1 |
|
04-Aug-2016 |
Icenowy Zheng <icenowy@aosc.xyz> |
mmc: sunxi: add support for A64 mmc controller A64 SoC features a MMC controller which need only the mod clock, and can calibrate delay by itself. This patch adds support for the new MMC controller IP core. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
2dd110b2 |
|
22-Aug-2016 |
Michael Weiser <michael.weiser@gmx.de> |
mmc: sunxi-mmc: change idma descriptor to __le32 The sunxi-mmc driver does not take into account the processor may be big endian when writing the DMA descriptors. This causes cards not to be detected when running a big-endian kernel. Change the descriptors for IDMA to use __le32 and ensure they are suitably swapped before writing. Tested successfully on the Cubieboard2. Signed-off-by: Michael Weiser <michael.weiser@gmx.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
63311bec |
|
23-Aug-2016 |
Jean-Francois Moine <moinejf@free.fr> |
mmc: sunxi: Check the value returned by clk_round_rate clk_round_rate() may return an error. Check it. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
b465646e |
|
30-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: sun4i / sun5i do not have sample clocks It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample clocks, so add a new sun7i-a20-mmc compatible and do not try to use sample clocks on sun4i / sun5i. Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks. Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare() calls to the sample clks as-is, without adding checks for them being NULL. All the clk_foo calls accept a NULL clk and will return success when called with a NULL clk. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
f2cecb70 |
|
30-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Factor out clock phase setting code into a helper function Add a sunxi_mmc_clk_set_phase() helper function. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
86a93317 |
|
30-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Introduce a sunxi_mmc_cfg struct Create a struct to hold the various model / compatible string dependend settings. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
4c5f4bf4 |
|
30-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Disable sample clks on remove When support for the sample clks was added calls to prepare_enable were added to the probe path, but matching calls to disable_unprepare were forgotten in the remove path, this fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
afefc102 |
|
29-May-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80 Now the the HS-DDR mode clock timings have been corrected, we can re-enable these modes on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
0175249e |
|
29-May-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Fix DDR MMC timings for A80 The MMC clock timings were incorrectly calculated, when the conversion from delay value to delay phase was done. The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR unusable. Unfortunately it seems different controllers on the same SoC have different timings. The new settings are taken from mmc2, which is commonly used with eMMC. The settings for the slower timing modes seem to work despite being wrong, so leave them be. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
2963070a |
|
26-Apr-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Disable eMMC HS-DDR (MMC_CAP_1_8V_DDR) for Allwinner A80 eMMC HS-DDR no longer works on the A80, despite it working when support for this developed. Disable it for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
f2c90c38 |
|
01-Feb-2016 |
Jaehoon Chung <jh80.chung@samsung.com> |
mmc: sunxi-mmc: remove the MMC_DATA_STREAM flag Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
aed26fca |
|
29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Now that clock delay settings for 8 bit DDR are correct, and vqmmc support is available, we can enable MMC_CAP_1_8V_DDR support. This enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching is not available. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
2a7aa63a |
|
29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support 8 bit eMMC DDR transfer modes Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed for 4 bit DDR transfers. Different clock delays are needed for 8 bit eMMC DDR, due to the increased module clock rate. For the A80 though, the same values for 4 bit and 8 bit are shared. The new values for the other SoCs were from A83T user manual's "new timing mode" default values, which describes them in clock phase, rather than delay periods. These values were used without any modification. They may not be correct, but they work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
2dcb305a |
|
29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support MMC_DDR52 timing modes DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays. Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD, and this number is visible in the capability macro, increase the clock rate upper limit to 52 MHz. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
f771f6e8 |
|
20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support vqmmc regulator eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc for driving output buffers. vqmmc also controls signaling voltage. Most boards we've seen use the same regulator for both, nevertheless the 2 have different usages, and should be set separately. This patch adds support for vqmmc regulator supply, including voltage switching. The MMC core can use this to try different signaling voltages for eMMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
4159215a |
|
20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a proper voltage for vmmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
0314cbd4 |
|
20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Document host init sequence sunxi_mmc_init_host() originated from Allwinner kernel sources. The magic numbers written to various registers was never documented. Add comments for values found in Allwinner user manuals. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
c1590dd8 |
|
22-Sep-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Add card busy detection Some sdio wifi modules have not been working reliable with the sunxi-mmc host code. This turns out to be caused by starting new io-rw commands while the card signals that it is still busy processing a previous command. This commit adds card-busy detection to the sunxi-mmc driver which together with recent core changes to check card-busy before starting io-rw commands fixes the wifi reliability issues on the Cubietruck and other sunxi boards using sdio wifi. Reported-by: Eugene K <sigintmailru@gmail.com> Suggested-by: Eugene K <sigintmailru@gmail.com> Cc: Eugene K <sigintmailru@gmail.com> Cc: Arend van Spriel <arend@broadcom.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
#
51424b28 |
|
23-Sep-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Fix clk-delay settings In recent allwinner kernel sources the mmc clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we are using. This commit brings us in sync with what allwinner does, fixing problems accessing sdcards on some A33 devices (and likely others). For pre sun9i hardware this makes the following changes: -At 400Khz change the sample delay from 7 to 0 (introduced in A31 sdk) -At 50 Mhz change the sample delay from 5 to 4 (introduced in A23 sdk) This also drops the clk-delay calculation for clocks > 50 MHz, we do not need this as we've: mmc->f_max = 50000000, and the delays in the old code were not correct (at 100 MHz the delay must be a multiple of 60, at 200 MHz a multiple of 120). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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7bb9c244 |
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12-Aug-2015 |
Michal Suchanek <hramrach@gmail.com> |
mmc: sunxi: fix timeout in sunxi_mmc_oclk_onoff The 250ms timeout is too short. On my system enabling the oclk takes under 50ms and disabling slightly over 100ms when idle. Under load disabling the clock can take over 350ms. This does not make mmc clock gating look like good option to have on sunxi but the system should not crash with mmc clock gating enabled nonetheless. This patch sets the timeout to 750ms. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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a4101dcb |
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10-Mar-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: add MMC_CAP_SDIO_IRQ capability When the sunxi mmc-controller code was initially merged MMC_CAP_SDIO_IRQ was not added to the host caps because of issues with some sdio wifi modules. It turns out that these issues have nothing to do with using sdio-irq support, they also happen with oob interrupts. Since the hardware supports sdio-irq everywhere, and since the one reason to not claim the capability is gone, add MMC_CAP_SDIO_IRQ to the default host caps. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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d34712d2 |
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24-Feb-2015 |
Arnd Bergmann <arnd@arndb.de> |
mmc: sunxi: avoid invalid pointer calculation The sunxi mmc driver tries to calculate a dma address by using pointer arithmetic, which causes a warning when dma_addr_t is wider than a pointer: drivers/mmc/host/sunxi-mmc.c: In function 'sunxi_mmc_init_idma_des': drivers/mmc/host/sunxi-mmc.c:296:35: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma; ^ To avoid this warning and to simplify the logic, this changes the code to avoid the cast and calculate the correct address manually. The behavior should be unchanged. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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9e71c589 |
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02-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Use devm_reset_control_get_optional() for reset control The reset control for the sunxi mmc controller is optional. Some newer platforms (sun6i, sun8i, sun9i) have it, while older ones (sun4i, sun5i, sun7i) don't. Use the properly stubbed _optional version so the driver does not fail to compile when RESET_CONTROLLER=n. This patch also adds a check for deferred probing on the reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: <stable@vger.kernel.org> # 3.16+ Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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de0673cd |
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16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Removing unused code Removing a relict from reverse engineering of the Android driver code in sunxi_mmc_clk_set_rate. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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0f0fcd37 |
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16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Correcting SDXC_HARDWARE_RESET bit Fixing the register name in sunxi_mmc_reset_host since the SDXC_HARDWARE_RESET bit is actually located within REG_GCTRL and not REG_CMDR as it was pointed out by Allwinner. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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dd9b3803 |
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16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Lock fix 1) Adding a comment in order to clarify the choice of the locks within sunxi_mmc_handle_manual_stop 2) As <lixiang@allwinnertech.com> has pointed out the wait_dma variable was not accessed within the spin lock block in sunxi_mmc_request and so (even if it should never happend) it would have theoretically been possible that some other function would access the variable at the same time as the function. This has been changed now and the function is using local variables outside the lock and copys the value over during the lock phase. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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e8a59049 |
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16-Dec-2014 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Fix setup of last descriptor of dma transfer The last descriptor might be the first descriptor as well, so use masking to add the LD (last descriptor) bit and drop the DIC (disable interrupt on completion) bit rather then hard assignment as hard assignment will override the FD (first descriptor) bit if there is only 1 descriptor. Also set the ER (end of ring) bit and clear buf_addr_ptr2 on the last descriptor, like the android kernel code does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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6c09bb85 |
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11-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
mmc: sunxi: Convert MMC driver to the standard clock phase API Now that we have proper support to use the generic phase API in our clock driver, switch the MMC driver to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
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05e07d8b |
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03-Oct-2014 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
mmc: sunxi: Remove unused includes of linux/clk-private.h Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3df01a93 |
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20-Aug-2014 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Declare ERASE capability Declare ERASE capability so we can use filesystems with the discard option and the fstrim tool. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2137f5d3 |
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12-Aug-2014 |
Peter Griffin <peter.griffin@linaro.org> |
mmc: remove .owner field for drivers using module_platform_driver This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3cbcb160 |
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12-May-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> [hdegoede@redhat.com: various cleanups and fixes] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Chris Ball <chris@printf.net> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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19b7f796 |
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12-May-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> [hdegoede@redhat.com: various cleanups and fixes] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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