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ba5bf51a |
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27-May-2020 |
Vishal Sagar <vishal.sagar@xilinx.com> |
media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready for image processing. Please refer to PG232 for details. The CSI2 Rx controller filters out all packets except for the packets with data type fixed in hardware. RAW8 packets are always allowed to pass through. It is also used to setup and handle interrupts and enable the core. It logs all the events in respective counters between streaming on and off. The driver supports only the video format bridge enabled configuration. Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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83268fa6 |
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08-Dec-2017 |
Dhaval Shah <dhaval23031987@gmail.com> |
media: xilinx: Use SPDX-License-Identifier SPDX-License-Identifier is used for the Xilinx Video IP and related drivers. [Added drivers/media/platform/xilinx/Kconfig] [Added drivers/media/platform/xilinx/Makefile] [Added include/dt-bindings/media/xilinx-vip.h] Signed-off-by: Dhaval Shah <dhaval23031987@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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a5562f65 |
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15-May-2013 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
[media] v4l: xilinx: Add Test Pattern Generator driver The TPG generates multiple static or dynamic test patterns. The driver currently hardcodes the pattern to the moving box pattern. Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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40ac9b19 |
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26-Mar-2014 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
[media] v4l: xilinx: Add Video Timing Controller driver The Video Timing Controller (VTC) includes a timing detector and/or a timing generator. Only the generator is currently supported. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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df330515 |
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15-May-2013 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
[media] v4l: xilinx: Add Xilinx Video IP core Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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