#
697d5cf0 |
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07-Mar-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
IB/qib: Drop redundant pci_enable_pcie_error_reporting() pci_enable_pcie_error_reporting() enables the device to send ERR_* Messages. Since f26e58bf6f54 ("PCI/AER: Enable error reporting when AER is native"), the PCI core does this for all devices during enumeration, so the driver doesn't need to do it itself. Remove the redundant pci_enable_pcie_error_reporting() call from the driver. Note that this only controls ERR_* Messages from the device. An ERR_* Message may cause the Root Port to generate an interrupt, depending on the AER Root Error Command register managed by the AER service driver. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Dennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Reviewed-by: Dennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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#
7eff3652 |
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08-Sep-2022 |
wangjianli <wangjianli@cdjrlc.com> |
RDMA/qib: fix repeated words in comments Delete the redundant word 'to'. Signed-off-by: wangjianli <wangjianli@cdjrlc.com> Link: https://lore.kernel.org/r/20220908132036.42355-1-wangjianli@cdjrlc.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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#
63f774c5 |
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21-Jan-2021 |
Lee Jones <lee.jones@linaro.org> |
RDMA/hw/qib/qib_pcie: Demote obvious kernel-doc abuse Fixes the following W=1 kernel build warning(s): drivers/infiniband/hw/qib/qib_pcie.c:190: warning: Function parameter or member 'dd' not described in 'qib_cache_msi_info' drivers/infiniband/hw/qib/qib_pcie.c:190: warning: Function parameter or member 'pos' not described in 'qib_cache_msi_info' Link: https://lore.kernel.org/r/20210121094519.2044049-12-lee.jones@linaro.org Cc: Dennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Cc: Mike Marciniszyn <mike.marciniszyn@cornelisnetworks.com> Cc: Doug Ledford <dledford@redhat.com> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: linux-rdma@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
df0e4de2 |
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21-Nov-2020 |
Christophe JAILLET <christophe.jaillet@wanadoo.fr> |
IB/qib: Use dma_set_mask_and_coherent to simplify code 'pci_set_dma_mask()' + 'pci_set_consistent_dma_mask()' can be replaced by an equivalent 'dma_set_mask_and_coherent()' which is much less verbose. Link: https://lore.kernel.org/r/20201121095127.1335228-1-christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Mike Marciniszyn <mike.marciniszyn@cornelisnetworks.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
4bdc0d67 |
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06-Jan-2020 |
Christoph Hellwig <hch@lst.de> |
remove ioremap_nocache and devm_ioremap_nocache ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
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#
d2c9d9ab |
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26-Nov-2018 |
Colin Ian King <colin.king@canonical.com> |
IB/qib: fix spelling mistake "colescing" -> "coalescing" There is a spelling mistake in the module description text, fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
62b36c3e |
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28-Sep-2018 |
Oza Pawandeep <poza@codeaurora.org> |
PCI/AER: Remove pci_cleanup_aer_uncorrect_error_status() calls After bfcb79fca19d ("PCI/ERR: Run error recovery callbacks for all affected devices"), AER errors are always cleared by the PCI core and drivers don't need to do it themselves. Remove calls to pci_cleanup_aer_uncorrect_error_status() from device driver error recovery functions. Signed-off-by: Oza Pawandeep <poza@codeaurora.org> [bhelgaas: changelog, remove PCI core changes, remove unused variables] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2055d1f0 |
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11-Oct-2017 |
Bart Van Assche <bvanassche@acm.org> |
IB/qib: Remove set-but-not-used variables Signed-off-by: Bart Van Assche <bart.vanassche@wdc.com> Tested-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
c4bc6156 |
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26-Sep-2017 |
Michael J. Ruhl <michael.j.ruhl@intel.com> |
IB/qib: Update QIB to use the latest PCI API The QIB PCI IRQ code uses an obsolete PCI API. Updating the code to use the new PCI IRQ API and any necessary changes because of the new API. Reviewed-by: Sebastian Sanchez <sebastian.sanchez@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
581d01aa |
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09-Jun-2017 |
Michael J. Ruhl <michael.j.ruhl@intel.com> |
IB/qib: Replace deprecated pci functions with new API pci_enable_msix_range() and pci_disable_msix() have been deprecated. Updating to the new pci_alloc_irq_vectors() interface. Reviewed-by: Sebastian Sanchez <sebastian.sanchez@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
2fd260f0 |
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24-Jan-2017 |
Michael S. Tsirkin <mst@redhat.com> |
PCI/AER: Remove unused .link_reset() callback No hardware seems to actually call .link_reset(), and no driver implements it as more than a nop stub. Drop mentions of the callback from everywhere. It's dropped from the documentation as well, but the doc really needs to be updated to reflect reality better (e.g., on PCIe, slot reset is the link reset). This will be done in a later patch. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
850d0872 |
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18-Dec-2016 |
Cao jin <caoj.fnst@cn.fujitsu.com> |
RDMA/qib: drop qib_pci_link_reset() In AER recovery, pci_error_handlers.link_reset() is never called, drop it now. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
8ffb4103 |
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29-Apr-2016 |
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> |
IB/qib: Use cache inhibitted and guarded mapping on powerpc The driver was requesting for a writethrough mapping. But with those flags we will end up with an SAO mapping because we now have memory conherence always enabled. ie, the existing mapping will end up with a WIMG value 0b1110 which is Strong Access Order. Update this to use cache inhibitted guarded mapping. Cc: Doug Ledford <dledford@redhat.com> Cc: Sean Hefty <sean.hefty@intel.com> Cc: Hal Rosenstock <hal.rosenstock@gmail.com> Cc: linux-rdma@vger.kernel.org Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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#
da12c1f6 |
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16-Jan-2015 |
Mike Marciniszyn <mike.marciniszyn@intel.com> |
IB/qib: Add blank line after declaration Upstream checkpatch now requires this. Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
a46a2802 |
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16-Jan-2015 |
Mike Marciniszyn <mike.marciniszyn@intel.com> |
IB/qib: Fix checkpatch warnings Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
bf3f043e |
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18-Feb-2014 |
Alexander Gordeev <agordeev@redhat.com> |
IB/qib: Use pci_enable_msix_range() instead of pci_enable_msix() As result of the deprecation of the MSI-X/MSI enablement functions pci_enable_msix() and pci_enable_msi_block(), all drivers using these two interfaces need to be updated to use the new pci_enable_msi_range() and pci_enable_msix_range() interfaces. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
03078633 |
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24-Sep-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
IB/qib: Drop qib_tune_pcie_caps() and qib_tune_pcie_coalesce() return values The callers of qib_tune_pcie_caps() and qib_tune_pcie_coalesce() don't check the return values, so this patch drops the return values altogether. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
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#
0ce0e62f |
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09-Sep-2013 |
Yijing Wang <wangyijing@huawei.com> |
IB/qib: Use pcie_set_mps() and pcie_get_mps() to simplify code Refactor qib_tune_pcie_caps(). Use pcie_get_mps(), pcie_set_mps(), pcie_get_readrq(), and pcie_set_readrq() to simplify the code. The PCI core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_word(). Remove the unused val2fld() and fld2val(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
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#
dcaa73dc |
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09-Sep-2013 |
Yijing Wang <wangyijing@huawei.com> |
IB/qib: Use pci_is_root_bus() to check whether it is a root bus Use pci_is_root_bus() instead of "if (bus->parent)" statement for better readability. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
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#
b29b0763 |
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08-Aug-2013 |
Yijing Wang <wangyijing@huawei.com> |
IB/qib: Clean up unnecessary MSI/MSI-X capability find PCI core will initialize device MSI/MSI-X capability in pci_msi_init_pci_dev(). So device drivers should use pci_dev->msi_cap/msix_cap to determine whether a device supports MSI/MSI-X instead of using pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX). Access to PCIe device config space again will consume more time. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
1d352035 |
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07-Sep-2012 |
Stephen Hemminger <shemminger@vyatta.com> |
make drivers with pci error handlers const Covers the rest of the uses of pci error handler. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
0921caf3 |
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24-Jul-2012 |
Jiang Liu <jiang.liu@huawei.com> |
IB/qib: Use PCI Express Capability accessors Use PCI Express Capability access functions to simplify qib driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
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#
7fac3301 |
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19-Jul-2012 |
Mike Marciniszyn <mike.marciniszyn@intel.com> |
IB/qib: checkpatch fixes Elminate some simple_strto* usage. checkpatch also noted pr_ conversations, which have been done as recommended. The pr_fmt() define is used to shorten line length. Other multi-line string warnings are also elmininated. Reviewed-by: Dean Luick <dean.luick@intel.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
f3331f88 |
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19-Jul-2012 |
Betty Dall <betty.dall@hp.com> |
IB/qib: Fix an incorrect log message There is a cut-and-paste typo in the function qib_pci_slot_reset() where it prints that the "link_reset" function is called rather than the "slot_reset" function. This makes the message misleading. Signed-off-by: Betty Dall <betty.dall@hp.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
a778f3fd |
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25-Feb-2012 |
Mike Marciniszyn <mike.marciniszyn@qlogic.com> |
IB/qib: Add logic for affinity hint Call irq_set_affinity_hint() to give userspace programs such as irqbalance the information to be able to distribute qib interrupts appropriately. The logic allocates all non-receive interrupts to the first CPU local to the HCA. Receive interrupts are allocated round robin starting with the second CPU local to the HCA with potential wrap back to the second CPU. This patch also adds a refinement to the name registered for MSI-X interrupts so that user level scripts can determine the device associated with the IRQs when there are multiple HCAs with a potentially different set of local CPUs. Signed-off-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
b6bfefb0 |
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12-Jan-2012 |
Mike Marciniszyn <mike.marciniszyn@qlogic.com> |
IB/qib: Roll back PCIe tuning change Commit 8d4548f2b ("IB/qib: Default some module parameters optimally") introduced an issue with older root complexes. They cannot handle the pcie_caps of 0x51 (MaxReadReq 4096, MaxPayload=256). A typical diagnostic in this situation reported by syslog contains the text: [PCIe Poisoned TLP][Send DMA memory read] Restore the module paramter default to zero with will avoid any changes in the root complex. Reviewed-by: Mark Debbage <mark.debbage@qlogic.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
8d4548f2 |
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23-Dec-2011 |
Mike Marciniszyn <mike.marciniszyn@qlogic.com> |
IB/qib: Default some module parameters optimally Minimize the need for users to have to set module parameters to get good performance. The following two parameters are changed: - rcvhdrcnt to twice the rcvegrcnt - pcie_caps=0x51 The rcvhdrcnt at twice the egrcount allows the preemptive NAK code during reception to function in 100% of the cases rather than a sender jiffies-based timeout. The pcie_caps default of 0x51 will set the proposed MaxPayload and MaxReceiveReqest to 256 and 4096 respectively. The capabilities on the root complex will be used to limit those values. Reviewed-by: Ram Vepa <ram.vepa@qlogic.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
e4dd23d7 |
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27-May-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
infiniband: Fix up module files that need to include module.h They had been getting it implicitly via device.h but we can't rely on that for the future, due to a pending cleanup so fix it now. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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#
7f27cda0 |
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27-Jun-2011 |
Jon Mason <jdmason@kudzu.us> |
IB/qib: Remove unnecessary read of PCI_CAP_ID_EXP The PCIE capability offset is saved during PCI bus walking. It will remove an unnecessary search in the PCI configuration space if this value is referenced instead of reacquiring it. Signed-off-by: Jon Mason <jdmason@kudzu.us> Acked-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
1c653357 |
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09-May-2011 |
Sergei Shtylyov <sshtylyov@ru.mvista.com> |
IB/qib: Use pci_dev->revision The driver reads PCI revision ID from the PCI configuration register while it's already stored by PCI subsystem in the revision field of struct pci_dev. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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#
2ca78d23 |
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25-Oct-2010 |
Jason Gunthorpe <jgg@ziepe.ca> |
IB/qib: clean up properly if pci_set_consistent_dma_mask() fails Clean up properly if pci_set_consistent_dma_mask() fails. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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#
5d26a1df |
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22-Oct-2010 |
Ralph Campbell <ralph.campbell@qlogic.com> |
IB/qib: Allow driver to load if PCIe AER fails Some PCIe root complex chip sets don't support advanced error reporting. Allow the driver to load OK if pci_enable_pcie_error_reporting() fails. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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#
fce24a9d |
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17-Jun-2010 |
Dave Olson <dave.olson@qlogic.com> |
IB/qib: Don't mark VL15 bufs as WC to avoid a rare 7322 chip problem Don't set write combining via PAT on the VL15 buffers to avoid a rare problem with unaligned writes from interrupt-flushed store buffers. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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#
f931551b |
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23-May-2010 |
Ralph Campbell <ralph.campbell@qlogic.com> |
IB/qib: Add new qib driver for QLogic PCIe InfiniBand adapters Add a low-level IB driver for QLogic PCIe adapters. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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