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124a9fbe |
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04-Mar-2024 |
wenglianfa <wenglianfa@huawei.com> |
RDMA/hns: Append SCC context to the raw dump of QPC SCCC (SCC Context) is a context with QP granularity that contains information about congestion control. Dump SCCC and QPC together to improve troubleshooting. When dumping raw QPC with rdmatool, there will be a total of 576 bytes data output, where the first 512 bytes is QPC and the last 64 bytes is SCCC. When congestion control is disabled, the 64 byte SCCC will be all 0. Example: $rdma res show qp -jpr [ { "ifindex": 0, "ifname": "hns_0", "data": [ 67,0,0,0... 512bytes 4,0,2... 64bytes] },... } ] Signed-off-by: wenglianfa <wenglianfa@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://lore.kernel.org/r/20240305055257.823513-1-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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6ec429d5 |
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01-Mar-2024 |
Junxian Huang <huangjunxian6@hisilicon.com> |
RDMA/hns: Support userspace configuring congestion control algorithm with QP granularity Currently, congestion control algorithm is statically configured in FW, and all QPs use the same algorithm(except UD which has a fixed configuration of DCQCN). This is not flexible enough. Support userspace configuring congestion control algorithm with QP granularity while creating QPs. If the algorithm is not specified in userspace, use the default one. Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://lore.kernel.org/r/20240301104845.1141083-1-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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5a872795 |
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16-Aug-2023 |
Chengchang Tang <tangchengchang@huawei.com> |
RDMA/hns: Support hns HW stats Support query hns HW stats for rdma-tool to help debugging. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://lore.kernel.org/r/20230816091812.2899366-3-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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0b5eed06 |
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20-Jul-2023 |
Junxian Huang <huangjunxian6@hisilicon.com> |
RDMA/hns: Remove VF extend configuration Remove VF extend configuration since the relative registers are configured in firmware currently. Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://lore.kernel.org/r/20230721025146.450831-3-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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f5a61344 |
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20-Jul-2023 |
Luoyouming <luoyouming@huawei.com> |
RDMA/hns: Support get XRCD number from firmware Support driver get the num of XRCD from firmware. Signed-off-by: Luoyouming <luoyouming@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://lore.kernel.org/r/20230721025146.450831-2-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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58caa2a5 |
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12-May-2023 |
Chengchang Tang <tangchengchang@huawei.com> |
RDMA/hns: Fix timeout attr in query qp for HIP08 On HIP08, the queried timeout attr is different from the timeout attr configured by the user. It is found by rdma-core testcase test_rdmacm_async_traffic: ====================================================================== FAIL: test_rdmacm_async_traffic (tests.test_rdmacm.CMTestCase) ---------------------------------------------------------------------- Traceback (most recent call last): File "./tests/test_rdmacm.py", line 33, in test_rdmacm_async_traffic self.two_nodes_rdmacm_traffic(CMAsyncConnection, self.rdmacm_traffic, File "./tests/base.py", line 382, in two_nodes_rdmacm_traffic raise(res) AssertionError Fixes: 926a01dc000d ("RDMA/hns: Add QP operations support for hip08 SoC") Link: https://lore.kernel.org/r/20230512092245.344442-2-huangjunxian6@hisilicon.com Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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faa63656 |
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04-Mar-2023 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Add new command to support query vf caps The current resource query for vf caps is driven by the driver, which is unreasonable. This patch adds a new command HNS_ROCE_OPC_QUERY_VF_CAPS_NUM to support obtaining vf caps information from firmware. Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Link: https://lore.kernel.org/r/20230304091555.2241298-2-xuhaoyue1@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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1d918553 |
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24-Dec-2022 |
Luoyouming <luoyouming@huawei.com> |
RDMA/hns: Support cqe inline in user space Enable the CQEIE field and configure the CQEIS field of QPC. And add compatibility handling. Link: https://lore.kernel.org/r/20221224102201.3114536-4-xuhaoyue1@hisilicon.com Signed-off-by: Luoyouming <luoyouming@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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667d6164 |
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26-Nov-2022 |
Chengchang Tang <tangchengchang@huawei.com> |
RDMA/hns: Fix error code of CMD The error code is fixed to EIO when CMD fails to excute. This patch converts the error status reported by firmware to linux errno. Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Link: https://lore.kernel.org/r/20221126102911.2921820-6-xuhaoyue1@hisilicon.com Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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487d6509 |
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26-Nov-2022 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Fix the gid problem caused by free mr After the hns roce driver is loaded, if you modify the mac address of the network port, the following error will appear: __ib_cache_gid_add: unable to add gid fe80:0000:0000:0000:4600:4dff:fe22:abb5 error=-28 hns3 0000:7d:00.0 hns_0: attr path_mtu(1) invalid while modify qp The reason for the error is that the gid being occupied will cause the failure to modify the gid. The gid is occupied by the loopback QP used by free mr. When the mac address is modified, the gid will change. If there is a busy QP at this time, the gid will not be released and the modification will fail. The QP of free mr is created using the ib interface. The ib interface will add a reference count to the gid, resulting in this error scenario. Considering that free mr is solving a bug in HIP08, not an actual business, it is not necessary to use ib interfaces. Fixes: 70f92521584f ("RDMA/hns: Use the reserved loopback QPs to free MR before destroying MPT") Link: https://lore.kernel.org/r/20221126102911.2921820-2-xuhaoyue1@hisilicon.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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9e272ed6 |
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24-Oct-2022 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Disable local invalidate operation When function reset and local invalidate are mixed, HNS RoCEE may hang. Before introducing the cause of the problem, two hardware internal concepts need to be introduced: 1. Execution queue: The queue of hardware execution instructions, function reset and local invalidate are queued for execution in this queue. 2.Local queue: A queue that stores local operation instructions. The instructions in the local queue will be sent to the execution queue for execution. The instructions in the local queue will not be removed until the execution is completed. The reason for the problem is as follows: 1. There is a function reset instruction in the execution queue, which is currently being executed. A necessary condition for the successful execution of function reset is: the hardware pipeline needs to empty the instructions that were not completed before; 2. A local invalidate instruction at the head of the local queue is sent to the execution queue. Now there are two instructions in the execution queue, the first is the function reset instruction, and the second is the local invalidate instruction, which will be executed in se quence; 3. The user has issued many local invalidate operations, causing the local queue to be filled up. 4. The user still has a new local operation command and is queuing to enter the local queue. But the local queue is full and cannot receive new instructions, this instruction is temporarily stored at the hardware pipeline. 5. The function reset has been waiting for the instruction before the hardware pipeline stage is drained. The hardware pipeline stage also caches a local invalidate instruction, so the function reset cannot be completed, and the instructions after it cannot be executed. These factors together cause the execution logic deadlock of the hardware, and the consequence is that RoCEE will not have any response. Considering that the local operation command may potentially cause RoCEE to hang, this feature is no longer supported. Fixes: e93df0108579 ("RDMA/hns: Support local invalidate for hip08 in kernel space") Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Link: https://lore.kernel.org/r/20221024083814.1089722-2-xuhaoyue1@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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6649b4a1 |
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22-Sep-2022 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Remove redundant 'max_srq_desc_sz' in caps The max_srq_desc_sz is defined in the code, but never used, so delete this redundant variable. Link: https://lore.kernel.org/r/20220922123315.3732205-10-xuhaoyue1@hisilicon.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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5436272c |
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22-Sep-2022 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Remove redundant 'num_mtt_segs' and 'max_extend_sg' The num_mtt_segs and max_extend_sg used to be used for HIP06, remove them since the HIP06 code has been removed. Link: https://lore.kernel.org/r/20220922123315.3732205-9-xuhaoyue1@hisilicon.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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064fd299 |
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22-Sep-2022 |
Guofeng Yue <yueguofeng@hisilicon.com> |
RDMA/hns: Remove unnecessary brackets when getting point Delete () when using & to obtain an address. Link: https://lore.kernel.org/r/20220922123315.3732205-4-xuhaoyue1@hisilicon.com Signed-off-by: Guofeng Yue <yueguofeng@hisilicon.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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3d67e7e2 |
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22-Aug-2022 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Support MR's restrack raw ops for hns driver The MR raw restrack attributes come from the queue context maintained by the ROCEE. For example: $ rdma res show mr dev hns_0 mrn 6 -dd -jp -r [ { "ifindex": 4, "ifname": "hns_0", "data": [ 1,0,0,0,2,0,0,0,0,3,0,0,0,0,2,0,0,0,0,0,32,0,0,0,2,0,0,0, 2,0,0,0,0,0,0,0 ] } ] Link: https://lore.kernel.org/r/20220822104455.2311053-8-liangwenpeng@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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40b4b79c |
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22-Aug-2022 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Remove redundant DFX file and DFX ops structure There is no need to use a dedicated DXF file and DFX structure to manage the interface of the query queue context. Link: https://lore.kernel.org/r/20220822104455.2311053-2-liangwenpeng@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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45baad7d |
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29-Aug-2022 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Remove the num_qpc_timer variable The bt number of qpc_timer of HIP09 increases compared with that of HIP08. Therefore, qpc_timer_bt_num and num_qpc_timer do not match. As a result, the driver may fail to allocate qpc_timer. So the driver needs to uniquely uses qpc_timer_bt_num to represent the bt number of qpc_timer. Fixes: 0e40dc2f70cd ("RDMA/hns: Add timer allocation support for hip08") Link: https://lore.kernel.org/r/20220829105021.1427804-4-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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55af9d49 |
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29-Aug-2022 |
Chengchang Tang <tangchengchang@huawei.com> |
RDMA/hns: Fix supported page size The supported page size for hns is (4K, 128M), not (4K, 2G). Fixes: cfc85f3e4b7f ("RDMA/hns: Add profile support for hip08 driver") Link: https://lore.kernel.org/r/20220829105021.1427804-2-liangwenpeng@huawei.com Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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2de949ab |
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14-Jul-2022 |
Haoyue Xu <xuhaoyue1@hisilicon.com> |
RDMA/hns: Recover 1bit-ECC error of RAM on chip Since ECC memory maintains a memory system immune to single-bit errors, add support for correcting the 1bit-ECC error, which prevents a 1bit-ECC error become an uncorrected type error. When a 1bit-ECC error happens in the internal ram of the ROCE engine, such as the QPC table, as a 1bit-ECC error caused by reading, the ROCE engine only corrects those 1bit ECC errors by writing. Link: https://lore.kernel.org/r/20220714134353.16700-6-liangwenpeng@huawei.com Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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f5c25465 |
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14-Jul-2022 |
Haoyue Xu <xuhaoyue1@hisilicon.com> |
RDMA/hns: Remove unused abnormal interrupt of type RAS The HNS NIC driver receives and handles the abnormal interrupt of the RAS type generated by ROCEE, and the HNS RDMA driver does not need to handle this type of interrupt. Therefore, delete unused codes in the HNS RDMA driver. Link: https://lore.kernel.org/r/20220714134353.16700-2-liangwenpeng@huawei.com Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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813c9802 |
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12-May-2022 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Use hr_reg_read() instead of remaining roce_get_xxx() To reduce the code size and make the code clearer, replace all roce_get_xxx() with hr_reg_read() to read the data fields. Link: https://lore.kernel.org/r/20220512080012.38728-3-liangwenpeng@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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82600b2d |
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12-May-2022 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Use hr_reg_xxx() instead of remaining roce_set_xxx() To reduce the code size and make the code clearer, replace all roce_set_xxx() with hr_reg_xxx() to write the data fields. Link: https://lore.kernel.org/r/20220512080012.38728-2-liangwenpeng@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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db5dfbf5 |
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29-Apr-2022 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Remove the num_cqc_timer variable The bt number of cqc_timer of HIP09 increases compared with that of HIP08. Therefore, cqc_timer_bt_num and num_cqc_timer do not match. As a result, the driver may fail to allocate cqc_timer. So the driver needs to uniquely uses cqc_timer_bt_num to represent the bt number of cqc_timer. Fixes: 0e40dc2f70cd ("RDMA/hns: Add timer allocation support for hip08") Link: https://lore.kernel.org/r/20220429093545.58070-1-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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70f92521 |
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09-Mar-2022 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Use the reserved loopback QPs to free MR before destroying MPT Before destroying MPT, the reserved loopback QPs send loopback IOs (one write operation per SL). Completing these loopback IOs represents that there isn't any outstanding request in MPT, then it's safe to destroy MPT. Link: https://lore.kernel.org/r/20220310042835.38634-1-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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8a3fa72f |
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31-Dec-2021 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Modify the hop num of HIP09 EQ to 1 HIP09 EQ does not support level 2 addressing. Link: https://lore.kernel.org/r/20211231101341.45759-3-liangwenpeng@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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31835593 |
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19-Nov-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Remove macros that are no longer used These macros are no longer used, so remove them. Link: https://lore.kernel.org/r/20211119140208.40416-9-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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3aecfc38 |
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19-Nov-2021 |
Xinhao Liu <liuxinhao5@hisilicon.com> |
RDMA/hns: Replace tab with space in the right-side comments There should be a space between the code and the comment on the right. Link: https://lore.kernel.org/r/20211119140208.40416-4-liangwenpeng@huawei.com Signed-off-by: Xinhao Liu <liuxinhao5@hisilicon.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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4ad81814 |
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09-Dec-2021 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Fix RNR retransmission issue for HIP08 Due to the discrete nature of the HIP08 timer unit, a requester might finish the timeout period sooner, in elapsed real time, than its responder does, even when both sides share the identical RNR timeout length included in the RNR Nak packet and the responder indeed starts the timing prior to the requester. Furthermore, if a 'providential' resend packet arrived before the responder's timeout period expired, the responder is certainly entitled to drop the packet silently in the light of IB protocol. To address this problem, our team made good use of certain hardware facts: 1) The timing resolution regards the transmission arrangements is 1 microsecond, e.g. if cq_period field is set to 3, it would be interpreted as 3 microsecond by hardware 2) A QPC field shall inform the hardware how many timing unit (ticks) constitutes a full microsecond, which, by default, is 1000 3) It takes 14ns for the processor to handle a packet in the buffer, so the RNR timeout length of 10ns would ensure our processing mechanism is disabled during the entire timeout period and the packet won't be dropped silently To achieve (3), we permanently set the QPC field mentioned in (2) to zero which nominally indicates every time tick is equivalent to a microsecond in wall-clock time; now, a RNR timeout period at face value of 10 would only last 10 ticks, which is 10ns in wall-clock time. It's worth noting that we adapt the driver by magnifying certain configuration parameters(cq_period, eq_period and ack_timeout)by 1000 given the user assumes the configuring timing unit to be microseconds. Also, this particular improvisation is only deployed on HIP08 since other hardware has already solved this issue. Fixes: cfc85f3e4b7f ("RDMA/hns: Add profile support for hip08 driver") Link: https://lore.kernel.org/r/20211209140655.49493-1-liangwenpeng@huawei.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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1a018278 |
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26-Aug-2021 |
Xinhao Liu <liuxinhao5@hisilicon.com> |
RDMA/hns: Delete unnecessary blank lines. Just delete unnecessary blank lines. Link: https://lore.kernel.org/r/1629985056-57004-8-git-send-email-liangwenpeng@huawei.com Signed-off-by: Xinhao Liu <liuxinhao5@hisilicon.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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4303e612 |
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25-Aug-2021 |
Junxian Huang <huangjunxian4@hisilicon.com> |
RDMA/hns: Bugfix for data type of dip_idx dip_idx is associated with qp_num whose data type is u32. However, dip_idx is incorrectly defined as u8 data in the hns_roce_dip struct, which leads to data truncation during value assignment. Fixes: f91696f2f053 ("RDMA/hns: Support congestion control type selection according to the FW") Link: https://lore.kernel.org/r/1629884592-23424-2-git-send-email-liangwenpeng@huawei.com Signed-off-by: Junxian Huang <huangjunxian4@hisilicon.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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0110a1ed |
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21-Aug-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove unsupport cmdq mode CMDQ support un-interrupt mode only, and firmware ignores this mode flag, so remove it. Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Link: https://lore.kernel.org/r/1629539607-33217-2-git-send-email-liangwenpeng@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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7ae61c5f |
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22-Jun-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Add window selection field of congestion control The window selection field is necessary for congestion control of HIP09, it is got from firmware and then filled into QPC. Some algorithms need it to decide whether to limit the number of windows. Fixes: f91696f2f053 ("RDMA/hns: Support congestion control type selection according to the FW") Link: https://lore.kernel.org/r/1624364163-44185-1-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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c2614b99 |
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18-Jun-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Clean definitions of EQC structure Remove unused members in EQ context structure. Fixes: 782832f25404 ("RDMA/hns: Simplify the function config_eqc()") Link: https://lore.kernel.org/r/1624011020-16992-7-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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57dba89a |
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21-Jun-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Clean SRQC structure definition Remove unused members in srq context structure. Link: https://lore.kernel.org/r/1624262443-24528-10-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
2b035e73 |
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21-Jun-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Use new interface to write DB related fields Use hr_write_reg() instead of roce_set_field(). Link: https://lore.kernel.org/r/1624262443-24528-9-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
fd9e3679 |
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21-Jun-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Use new interface to write FRMR fields Use "hr_reg_write" to replace "roce_set_filed". Link: https://lore.kernel.org/r/1624262443-24528-8-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
f778bf1b |
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21-Jun-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Use new interface to get CQE fields WQE_INDEX and OPCODE and QPN of CQE use redundant masks. Just remove them. Link: https://lore.kernel.org/r/1624262443-24528-7-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
f0cb411a |
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21-Jun-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Use new interface to modify QP context Fill all QPC fileds with hr_reg_*() instead of roce_set_*(). SQPN is used for HIP08 ES only, it should be removed. Link: https://lore.kernel.org/r/1624262443-24528-6-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
f6fcd28d |
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21-Jun-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Use new interface to write CQ context. Use hr_reg_*() to write CQ context, it's simpler than roce_set_*(). Link: https://lore.kernel.org/r/1624262443-24528-5-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
7e78dd81 |
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11-Jun-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Clear extended doorbell info before using Both of HIP08 and HIP09 require the extended doorbell information to be cleared before being used. Fixes: 6b63597d3540 ("RDMA/hns: Add TSQ link table support") Link: https://lore.kernel.org/r/1623392089-35639-1-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
61b460d1 |
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01-Jun-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Support getting max QP number from firmware All functions of HIP09's ROCEE share on-chip resources for all QPs, the driver needs configure the resource index and number for each function during the init stage. Link: https://lore.kernel.org/r/1622541427-42193-1-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
3f0d979e |
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24-May-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Refactor capability configuration flow of VF The capbability configurations of PFs and VFs are coupled. Decoupling them by abstracting some functions and reorganizing the configuration process. Link: https://lore.kernel.org/r/1621860428-58009-1-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
21090b5d |
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19-May-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove Receive Queue of CMDQ The CRQ of CMDQ is unused, so remove code about it. Link: https://lore.kernel.org/r/1621482876-35780-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
b6989da8 |
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19-May-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Refactor extend link table allocation The timeout link table works in HIP08 ES version and the hns driver only support the CS version for HIP08, so delete the related code. Then simplify the buffer allocation for link table to make the code more readable. Link: https://lore.kernel.org/r/1621481751-27375-1-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
719d1341 |
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06-Apr-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Remove duplicated hem page size config code Remove duplicated code for setting hem page size in PF and VF. Link: https://lore.kernel.org/r/1617715514-29039-7-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
0b567cde |
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06-Apr-2021 |
Wei Xu <xuwei5@hisilicon.com> |
RDMA/hns: Enable RoCE on virtual functions Introduce the VF support by adding code changes to allow VF PCI device initialization, assgining the reserved resource of the PF to the active VFs, setting the default abilities, applying the interruptions, resetting and reducing the default QP/GID number to aovid exceeding the hardware limitation. Link: https://lore.kernel.org/r/1617715514-29039-6-git-send-email-liweihang@huawei.com Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Shengming Shu <shushengming1@huawei.com> Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
2a424e1d |
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06-Apr-2021 |
Wei Xu <xuwei5@hisilicon.com> |
RDMA/hns: Reserve the resource for the VFs Query the resource including EQC/SMAC/SGID from the firmware in the PF and distribute fairly among all the functions belong to the PF. Link: https://lore.kernel.org/r/1617715514-29039-4-git-send-email-liweihang@huawei.com Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Shengming Shu <shushengming1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
5b03a422 |
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06-Apr-2021 |
Wei Xu <xuwei5@hisilicon.com> |
RDMA/hns: Query the number of functions supported by the PF Query how many functions are supported by the PF from the FW and store it in the hns_roce_dev structure which will be used to support the configuration of virtual functions. Link: https://lore.kernel.org/r/1617715514-29039-3-git-send-email-liweihang@huawei.com Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Shengming Shu <shushengming1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
0fb46da0 |
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06-Apr-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Simplify function's resource related command Use hr_reg_write/read() to simplify codes about configuring function's resource. And because the design of PF/VF fields is same, they can be defined only once. Link: https://lore.kernel.org/r/1617715514-29039-2-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
782832f2 |
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02-Apr-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Simplify the function config_eqc() Use "hr_reg_write" replace "roce_set_filed". Link: https://lore.kernel.org/r/1617354454-47840-9-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
495c2480 |
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02-Apr-2021 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Add XRC subtype in QPC and XRC type in SRQC A field to distuiguish basic SRQ from XRC SRQ in SRQC and a field in QPC to determine whether a QP is XRC TGT QP or XRC INI QP are missing. Fixes: 32548870d438 ("RDMA/hns: Add support for XRC on HIP09") Link: https://lore.kernel.org/r/1617354454-47840-8-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
2371efab |
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02-Apr-2021 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Delete redundant abnormal interrupt status The hardware supports only two types of abnormal interrupts. Fixes: a5073d6054f7 ("RDMA/hns: Add eq support of hip08") Link: https://lore.kernel.org/r/1617354454-47840-5-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
0835cf58 |
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01-Apr-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Support more return types of command queue Add error code definition according to the return code from firmware to help find out more detailed reasons why a command fails to be sent. Link: https://lore.kernel.org/r/1617262341-37571-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
704d68f5 |
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27-Mar-2021 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Reorganize doorbell update interfaces for all queues The doorbell update interfaces are very similar for different queues, such as SQ, RQ, SRQ, CQ and EQ. So reorganize these code and also fix some inappropriate naming. Link: https://lore.kernel.org/r/1616840738-7866-3-git-send-email-liweihang@huawei.com Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
8115f974 |
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26-Mar-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Simplify command fields for HEM base address configuration Use hr_reg_write() instead of roce_set_field() to simplify codes about configuring HEM BA. Link: https://lore.kernel.org/r/1616815294-13434-6-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
ee82e688 |
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26-Mar-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Refactor reset state checking flow The 'HNS_ROCE_OPC_QUERY_MB_ST' command will response the mailbox complete status and hardware busy flag, and the complete status is only valid when the busy flag is 0, so it's better to query these two fields at a time rather than separately. Link: https://lore.kernel.org/r/1616815294-13434-4-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
f91696f2 |
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25-Mar-2021 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Support congestion control type selection according to the FW The type of congestion control algorithm includes DCQCN, LDCP, HC3 and DIP. The driver will select one of them according to the firmware when querying PF capabilities, and then set the related configuration fields into QPC. Link: https://lore.kernel.org/r/1616679236-7795-3-git-send-email-liweihang@huawei.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
e079d87d |
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25-Mar-2021 |
Wei Xu <xuwei5@hisilicon.com> |
RDMA/hns: Support query information of functions from FW Add a new type of command to query mac id of functions from the firmware, it is used to select the template of congestion algorithm. More info will be supported in the future. Link: https://lore.kernel.org/r/1616679236-7795-2-git-send-email-liweihang@huawei.com Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Shengming Shu <shushengming1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
32548870 |
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03-Mar-2021 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Add support for XRC on HIP09 The HIP09 supports XRC transport service, it greatly saves the number of QPs required to connect all processes in a large cluster. Link: https://lore.kernel.org/r/1614826558-35423-1-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
bf656b02 |
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09-Feb-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Adjust definition of FRMR fields FRMR is not well-supported on HIP08, it is re-designed for HIP09 and the position of related fields is changed. Then the ULPs should be forbidden to use FRMR on older hardwares. Link: https://lore.kernel.org/r/1612924424-28217-1-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
292b3352 |
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07-Feb-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Adjust fields and variables about CMDQ tail/head The register 0x07014 is actually the head pointer of CMDQ, and 0x07010 means tail pointer. Current definitions are confusing, so rename them and related variables. The next_to_use of structure hns_roce_v2_cmq_ring has the same semantics as head, merge them into one member. The next_to_clean of structure hns_roce_v2_cmq_ring has the same semantics as tail. After deleting next_to_clean, tail should also be deleted. Link: https://lore.kernel.org/r/1612688143-28226-5-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
563aeb22 |
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07-Feb-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove redundant operations on CMDQ CMDQ works serially, after each successful transmission, the head and tail pointers will be equal, so there is no need to check whether the queue is full. At the same time, since the descriptor of each transmission is new, there is no need to perform a cleanup operation. Then, the field named next_to_clean in structure hns_roce_v2_cmq_ring is redundant. Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Link: https://lore.kernel.org/r/1612688143-28226-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
22955723 |
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07-Feb-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove unused member and variable of CMDQ last_status of structure hns_roce_v2_cmq has never been used, and the variable named 'complete' in __hns_roce_cmq_send() is meaningless. Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Link: https://lore.kernel.org/r/1612688143-28226-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
01584a5e |
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30-Jan-2021 |
Yixing Liu <liuyixing1@huawei.com> |
RDMA/hns: Add support of direct wqe Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. Link: https://lore.kernel.org/r/1611997513-27107-1-git-send-email-liweihang@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
3f31c412 |
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30-Jan-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Use new interfaces to write SRQC Use new register operation interfaces to simplify the process of write SRQ Context. Link: https://lore.kernel.org/r/1611997090-48820-9-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
9dd05247 |
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30-Jan-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Allocate one more recv SGE for HIP08 The RQ/SRQ of HIP08 needs one special sge to stop receive reliably. So the driver needs to allocate at least one SGE when creating RQ/SRQ and ensure that at least one SGE is filled with the special value during post_recv. Besides, the kernel driver should only do this for kernel ULP. For userspace ULP, the userspace driver will allocate the reserved SGE in buffer, and the kernel driver just needs to pin the corresponding size of memory based on the userspace driver's requirements. Link: https://lore.kernel.org/r/1611997090-48820-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
dc504774 |
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23-Jan-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Use new interface to set MPT related fields Achieve hr_reg_write() to simply the codes to fill fields. Link: https://lore.kernel.org/r/1611395282-991-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
dc93a0d9 |
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10-Dec-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Fix coding style issues Just format the code without modifying anything, including fixing some redundant and missing blanks and spaces and changing the variable definition order. Link: https://lore.kernel.org/r/1607650657-35992-8-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
f93c39bc |
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26-Nov-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Add support for QP stash Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. It can be used to improve the performance by increasing the hit ratio of L3 cache. QPs need to enable stash by default. Link: https://lore.kernel.org/r/1606374251-21512-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
bfefae9f |
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26-Nov-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Add support for CQ stash Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. It can be used to improve the performance by increasing the hit ratio of L3 cache. CQs need to enable stash by default. Link: https://lore.kernel.org/r/1606374251-21512-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
534c9bdb |
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16-Nov-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Simplify process of filling UD SQ WQE There are some codes can be simplified or encapsulated in set_ud_wqe() to make them easier to be understand. Link: https://lore.kernel.org/r/1605526408-6936-6-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
148f904c |
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16-Nov-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Remove the portn field in UD SQ WQE This field in UD WQE in not used by hardware. Fixes: 7bdee4158b37 ("RDMA/hns: Fill sq wqe context of ud type in hip08") Link: https://lore.kernel.org/r/1605526408-6936-5-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
ebed7b7c |
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26-Nov-2020 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Fix wrong field of SRQ number the device supports The SRQ capacity is got from the firmware, whose field should be ended at bit 19. Fixes: ba6bb7e97421 ("RDMA/hns: Add interfaces to get pf capabilities from firmware") Link: https://lore.kernel.org/r/1606382812-23636-1-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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#
32053e58 |
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23-Oct-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Add support for filling GMV table Add a interface to fill GMV(SGID/SMAC/VLAN) table for HIP09, all of above source address information is stored as an entry in GMV table. The users just need to provide the index to the hardware when POST SEND. Link: https://lore.kernel.org/r/1603508836-33054-3-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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d6d91e46 |
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23-Oct-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Add support for configuring GMV table HIP09 supports to store SGID/SMAC/VLAN together in a table named GMV. The driver needs to allocate memory for it and tell the information about this region to hardware. Link: https://lore.kernel.org/r/1603508836-33054-2-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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30b70788 |
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10-Sep-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Support inline data in extented sge space for RC HIP08 supports RC inline up to size of 32 Bytes, and all data should be put into SQWQE. For HIP09, this capability is extended to 1024 Bytes, if length of data is longer than 32 Bytes, they will be filled into extended sge space. Link: https://lore.kernel.org/r/1599744069-9968-1-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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172505cf |
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19-Sep-2020 |
Jiaran Zhang <zhangjiaran@huawei.com> |
RDMA/hns: Add check for the validity of sl configuration According to the RoCE v1 specification, the sl (service level) 0-7 are mapped directly to priorities 0-7 respectively, sl 8-15 are reserved. The driver should verify whether the the value of sl is larger than 7, if so, an exception should be returned. Fixes: 926a01dc000d ("RDMA/hns: Add QP operations support for hip08 SoC") Link: https://lore.kernel.org/r/1600509802-44382-5-git-send-email-liweihang@huawei.com Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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3cb2c996 |
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16-Sep-2020 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Add support for SCCC in size of 64 Bytes For HIP09, size of SCCC (Soft Congestion Control Context) is increased to 64 Bytes from 32 Bytes. The hardware will get the configuration of SCCC from driver instead of using a fixed value. Link: https://lore.kernel.org/r/1600245806-56321-5-git-send-email-liweihang@huawei.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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98912ee8 |
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16-Sep-2020 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Add support for QPC in size of 512 Bytes The new version of RoCEE supports using QPC in size of 256B or 512B, so that HIP09 can supports new congestion control algorithms by using QPC in larger size. Link: https://lore.kernel.org/r/1600245806-56321-4-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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09a5f210 |
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16-Sep-2020 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Add support for CQE in size of 64 Bytes The new version of RoCEE supports using CQE in size of 32B or 64B. The performance of bus can be improved by using larger size of CQE. Link: https://lore.kernel.org/r/1600245806-56321-3-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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247fc16d |
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16-Sep-2020 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Add support for EQE in size of 64 Bytes The new version of RoCEE supports using CEQE in size of 4B or 64B, AEQE in size of 16B or 64B. The performance of bus can be improved by using larger size of EQE. Link: https://lore.kernel.org/r/1600245806-56321-2-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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6da06c62 |
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19-Aug-2020 |
Weihang Li <liweihang@huawei.com> |
Revert "RDMA/hns: Reserve one sge in order to avoid local length error" This patch caused some issues on SEND operation, and it should be reverted to make the drivers work correctly. There will be a better solution that has been tested carefully to solve the original problem. This reverts commit 711195e57d341e58133d92cf8aaab1db24e4768d. Fixes: 711195e57d34 ("RDMA/hns: Reserve one sge in order to avoid local length error") Link: https://lore.kernel.org/r/1597829984-20223-1-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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395f2e8f |
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28-Jul-2020 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Fix the unneeded process when getting a general type of CQE error If the hns ROCEE reports a general error CQE (types not specified by the IB General Specifications), it's no need to change the QP state to error, and the driver should just skip it. Fixes: 7c044adca272 ("RDMA/hns: Simplify the cqe code of poll cq") Link: https://lore.kernel.org/r/1595932941-40613-8-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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57005c96 |
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28-Jul-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove redundant hardware opcode definitions HNS_ROCE_SQ_OPCODE_XXXs and HNS_ROCE_V2_WQE_OP_XXXs have same values, so remove a set of redundant definitions. In addition, remove the suffix of HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE. Link: https://lore.kernel.org/r/1595932941-40613-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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14ba8730 |
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22-May-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Remove redundant type cast for general pointers There is no need to do a type cast on genernal pointers, they could be assigned to any type of variables. In addition, optimize initialization of some variables and adjust order of them. Link: https://lore.kernel.org/r/1590152579-32364-2-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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711195e5 |
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08-May-2020 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Reserve one sge in order to avoid local length error When rq/srq sge length is smaller than sq sge length, it will produce a local length error and may cause the bus to hang. Therefore, for rq wqe and srq wqe, one reserved sge pointing to a reserved mr is used to avoid this error. Link: https://lore.kernel.org/r/1588931159-56875-10-git-send-email-liweihang@huawei.com Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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30661322 |
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05-May-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Extend capability flags for HIP08_C 12 bits is not enough for HIP08_C, so extend a new field in length of 16 bits for it. Link: https://lore.kernel.org/r/1588674607-25337-3-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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23190b8f |
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30-Apr-2020 |
Weihang Li <liweihang@huawei.com> |
RDMA/hns: Fix comments with non-English symbols There is a comments with some chinese semicolons that cause encoding issues each time hns_roc_hw_v2.h was modified from a IDE. So fix this by using correct symbols. Link: https://lore.kernel.org/r/1588242691-12913-2-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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90e735ae |
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25-Mar-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Modify the mask of QP number for CQE of hip08 The hip08 supports up to 1M QPs, so the qpn mask of cqe should be modified. Link: https://lore.kernel.org/r/1585194018-4381-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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019cd05c |
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25-Mar-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Reduce the maximum number of extend SGE per WQE Just reduce the default number to 64 for backward compatibility, the driver can still get this configuration from the firmware. Link: https://lore.kernel.org/r/1585194018-4381-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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f91b9196 |
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19-Mar-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Remove definition of cq doorbell structure The struct hns_roce_v2_cq_db is unused, it should be removed. Link: https://lore.kernel.org/r/1584674622-52773-7-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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fd72926c |
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19-Mar-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Adjust the qp status value sequence of the hardware Interchange SQD and SQE to match the protocol. Link: https://lore.kernel.org/r/1584674622-52773-6-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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7db82697 |
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14-Jan-2020 |
Jiaran Zhang <zhangjiaran@huawei.com> |
RDMA/hns: Add support for extended atomic in userspace To support extended atomic operations including cmp & swap and fetch & add of 8 bytes, 16 bytes, 32 bytes, 64 bytes in userspace, some field in qpc should be configured. Link: https://lore.kernel.org/r/1579052546-11746-1-git-send-email-liweihang@huawei.com Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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80a78570 |
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11-Jan-2020 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Get pf capabilities from firmware Get pf capabilities from firmware according to different hardwares, if it fails, all capabilities will be set with a default value. Link: https://lore.kernel.org/r/1578738761-3176-4-git-send-email-liweihang@huawei.com Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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ba6bb7e9 |
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11-Jan-2020 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add interfaces to get pf capabilities from firmware pf capabilities are set by default for hip08 previously which should depends on different types of hardware. So add new interfaces to get them from firmware. Link: https://lore.kernel.org/r/1578738761-3176-3-git-send-email-liweihang@huawei.com Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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887803db |
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24-Oct-2019 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Bugfix for qpc/cqc timer configuration qpc/cqc timer entry size needs one page, but currently they are fixedly configured to 4096, which is not appropriate in 64K page scenarios. So they should be modified to PAGE_SIZE. Fixes: 0e40dc2f70cd ("RDMA/hns: Add timer allocation support for hip08") Link: https://lore.kernel.org/r/1571908917-16220-3-git-send-email-liweihang@hisilicon.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Weihang Li <liweihang@hisilicon.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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e075da5e |
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21-Aug-2019 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Add reset process for function-clear If the hardware is resetting, the driver should not perform the mailbox operation.Function-clear needs to add relevant judgment. Signed-off-by: Lang Cheng <chenglang@huawei.com> Link: https://lore.kernel.org/r/1566393276-42555-7-git-send-email-oulijun@huawei.com Signed-off-by: Doug Ledford <dledford@redhat.com>
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90c559b1 |
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21-Aug-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Remove the some magic number Here uses the meaningful macro instead of the magic number for readability. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Lang Chen <chenglang@huawei.com> Link: https://lore.kernel.org/r/1566393276-42555-5-git-send-email-oulijun@huawei.com Signed-off-by: Doug Ledford <dledford@redhat.com>
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2288b3b3 |
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08-Aug-2019 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Remove unnessary init for cmq reg There is no need to init the enable bit of cmq. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Link: https://lore.kernel.org/r/1565276034-97329-5-git-send-email-oulijun@huawei.com Signed-off-by: Doug Ledford <dledford@redhat.com>
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89a6da3c |
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14-Jun-2019 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: reset function when removing module During removing the driver, we needs to notify the roce engine to stop working immediately,and symmetrically recycle the hardware resources requested during initialization. The hardware provides a command called function clear that can package these operations,so that the driver can only focus on releasing resources that applied from the operating system. This patch implements the call of this command. Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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2a3d923f |
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24-May-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Replace magic numbers with #defines This patch makes the code more readable by removing magic numbers. Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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0502849d |
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24-May-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update CQE specifications According to hip08 UM, the maximum number of CQEs supported by each CQ is 4M. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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e1c9a0dc |
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01-Apr-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Dump detailed driver-specific CQ This patch adds support of resource track for hip08 and take dumping cq context state used for debugging as an example. More resources track supports for hns driver will be added in future. The output should be as follows. $ rdma res show cq dev hnseth0 -d dev hnseth0 cqe 1023 users 2 poll-ctx WORKQUEUE pid 0 comm [ib_core] drv_state 2 drv_ceq n 0 drv_cqn 0 drv_hopnum 1 drv_pi 0 drv_ci 0 drv_coalesce 0 drv_period 0 drv_cnt 0 Signed-off-by: Tao Tian <tiantao6@huawei.com> Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: chenglang <chenglang@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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834fa8cf |
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23-Feb-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update the range of raq_psn field of qp context According to hip08 UM(User Manual), the raq_psn field size is [23:0]. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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3e394f94 |
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16-Feb-2019 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Modify qp&cq&pd specification according to UM Accroding to hip08's limitation, qp&cq specification is 1M, mtpt specification 1M in kernel space. Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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d3743fa9 |
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03-Feb-2019 |
Wei Hu (Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Fix the chip hanging caused by sending doorbell during reset On hi08 chip, There is a possibility of chip hanging when sending doorbell during reset. We can fix it by prohibiting doorbell during reset. Fixes: 2d40788825ac ("RDMA/hns: Add support for processing send wr and receive wr") Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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6a04aed6 |
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03-Feb-2019 |
Wei Hu (Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Fix the chip hanging caused by sending mailbox&CMQ during reset On hi08 chip, There is a possibility of chip hanging and some errors when sending mailbox & doorbell during reset. We can fix it by prohibiting mailbox and doorbell during reset and reset occurred to ensure that hardware can work normally. Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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d061effc |
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03-Feb-2019 |
Wei Hu (Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Fix the Oops during rmmod or insmod ko when reset occurs In the reset process, the hns3 NIC driver notifies the RoCE driver to perform reset related processing by calling the .reset_notify() interface registered by the RoCE driver in hip08 SoC. In the current version, if a reset occurs simultaneously during the execution of rmmod or insmod ko, there may be Oops error as below: Internal error: Oops: 86000007 [#1] PREEMPT SMP Modules linked in: hns_roce(O) hns3(O) hclge(O) hnae3(O) [last unloaded: hns_roce_hw_v2] CPU: 0 PID: 14 Comm: kworker/0:1 Tainted: G O 4.19.0-ge00d540 #1 Hardware name: Huawei Technologies Co., Ltd. Workqueue: events hclge_reset_service_task [hclge] pstate: 60c00009 (nZCv daif +PAN +UAO) pc : 0xffff00000100b0b8 lr : 0xffff00000100aea0 sp : ffff000009afbab0 x29: ffff000009afbab0 x28: 0000000000000800 x27: 0000000000007ff0 x26: ffff80002f90c004 x25: 00000000000007ff x24: ffff000008f97000 x23: ffff80003efee0a8 x22: 0000000000001000 x21: ffff80002f917ff0 x20: ffff8000286ea070 x19: 0000000000000800 x18: 0000000000000400 x17: 00000000c4d3225d x16: 00000000000021b8 x15: 0000000000000400 x14: 0000000000000400 x13: 0000000000000000 x12: ffff80003fac6e30 x11: 0000800036303000 x10: 0000000000000001 x9 : 0000000000000000 x8 : ffff80003016d000 x7 : 0000000000000000 x6 : 000000000000003f x5 : 0000000000000040 x4 : 0000000000000000 x3 : 0000000000000004 x2 : 00000000000007ff x1 : 0000000000000000 x0 : 0000000000000000 Process kworker/0:1 (pid: 14, stack limit = 0x00000000af8f0ad9) Call trace: 0xffff00000100b0b8 0xffff00000100b3a0 hns_roce_init+0x624/0xc88 [hns_roce] 0xffff000001002df8 0xffff000001006960 hclge_notify_roce_client+0x74/0xe0 [hclge] hclge_reset_service_task+0xa58/0xbc0 [hclge] process_one_work+0x1e4/0x458 worker_thread+0x40/0x450 kthread+0x12c/0x130 ret_from_fork+0x10/0x18 Code: bad PC value In the reset process, we will release the resources firstly, and after the hardware reset is completed, we will reapply resources and reconfigure the hardware. We can solve this problem by modifying both the NIC and the RoCE driver. We can modify the concurrent processing in the NIC driver to avoid calling the .reset_notify and .uninit_instance ops at the same time. And we need to modify the RoCE driver to record the reset stage and the driver's init/uninit state, and check the state in the .reset_notify, .init_instance. and uninit_instance functions to avoid NULL pointer operation. Fixes: cb7a94c9c808 ("RDMA/hns: Add reset process for RoCE in hip08") Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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0e40dc2f |
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18-Dec-2018 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Add timer allocation support for hip08 This patch adds qpc timer and cqc timer allocation support for hardware timeout retransmission in kernel space driver. Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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aa84fa18 |
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18-Dec-2018 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Add SCC context clr support for hip08 This patch adds SCC context clear support for DCQCN in kernel space driver. Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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6a157f7d |
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18-Dec-2018 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Add SCC context allocation support for hip08 This patch adds SCC context allocation and initialization support for DCQCN in kernel space driver. Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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0c1c3880 |
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08-Dec-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Bugfix for RoCE loopback test This patch implements a cmdq to enable the loopback of ssu module according to the modified hardware desgin. The ssu consists of ingress unit, packet buffer and programmable packet process unit. if the loopback bit of ssu is not enabled, the roce packet with loopback bit will fail. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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f747b689 |
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08-Dec-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update posting & querying mailbox This patch updates the implementation of the mailbox command interface by using command queue instead of operating registers. With this update, the software can be well decoupled with the hardware. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
c7bcb134 |
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24-Nov-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add SRQ support for hip08 kernel mode This patch implements the SRQ(Share Receive Queue) verbs and update the poll cq verbs to deal with SRQ complentions. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
5c1f167a |
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24-Nov-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Init SRQ table for hip08 This patch inits hem resource for SRQ table, includes SRQWQE and SRQWQE index resource. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
d16da119 |
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24-Nov-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Eanble SRQ capacity for hip08 This patch configures the flags for enabling the SRQ(Share Receive Queue) capacity as well as update the verb of querying device for setting srq specifications. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
68a997c5 |
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05-Oct-2018 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Add FRMR support for hip08 This patch adds fast register physical memory region (FRMR) support for hip08. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
caf3e406 |
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30-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add vlan enable bit for hip08 In order to extend vlan device range, the design add two field of qp context for checking vlan packet in sender and in recevicer. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
2362ccee |
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30-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update some fields of qp context The hip08 hardware has two version. the version id are 0x20 and 0x21 according to the pci revision. It needs to adjust some fields for extending new features. The specific updates include: 1. Add some fields for supporting new features by enabling some reserved fields in 0x20 version. 2. remove some fields which the user is not visiable in order to support the extend features. 3. Init some fields with zero. These updates is compatible with 0x20 version. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
3a63c964 |
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30-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update some attributes of the RoCE device According to the IB protocol definition, the driver needs to show the correct device information and the information will be queryed by device attribute. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
05ad5482 |
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30-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Limit the size of extend sge of sq The hip08 split two hardware version. The version id are 0x20 and 0x21 according to the PCI revison. The max size of extend sge of sq is limited to 2M for 0x20 version and 8M for 0x21 version. It may be exceeded to 2M according to the algorithm that compute the product of wqe count and extend sge number of every wqe. But the product always less than 8M. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
06ef0ee4 |
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30-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Bugfix for reserved qp number It needs to include two special qps for every port. The hip08 have four ports and the all reserved qp numbers are eight. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
c7c28191 |
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23-Sep-2018 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Add MW support for hip08 This patch adds memory window (mw) support in the kernel space. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
8320deb8 |
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22-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add enable judgement for UD vlan According to the hardware modification, the vlan of the UD packet is based on the ud_vlan_en field of the UD wqe to determine whether to add a vlan header to the UD packet. The ud_vlan_en field is filled by the driver according to the net device. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
944e6409 |
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22-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add CM of vlan device support This patch mainly sets the vlan_id field in the WC for rdma_listen() to work over vlan. This is required by ib_init_ah_attr_from_wc() which is called by the CM REQ handler. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
384f8818 |
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22-Sep-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Add atomic support This patch adds atomic operations for hip08, includes fetchadd and cmpswap operation. In order to enable atomic, the driver needs to do the following steps: 1. Enable the atomic caps for RoCE device 2. Post the wqe context of atomic type 3. Configure the atomic type of mtpt Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
426c4146 |
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30-Jul-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Use macro instead of magic number This patch mainly uses CMD_CSQ_DESC_NUM instead of magic number in order to improve readability. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
c8e46f8d |
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30-Jul-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Assign the value for vlan field of qp context This patch mainly fills the correct value into the vlan id field of qp context as well as update the vlan field name according to the latest hardware user manual. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
0c4a0e29 |
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25-Jul-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update the data type of immediate data Because the data structure of hip08 is little endian, it needs to fix the immediate field of wqe and cqe into __le32. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
e8e8b652 |
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09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Update the implementation of set_mac This patch updates the implementation of set_mac by using command queue instead of directly writing registers. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
4db134a3 |
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09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Update the implementation of set_gid This patch updates the implementation of set_gid by using command queue instead of directly writing registers. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
ded58ff9 |
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09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Add TPQ link table support In hip08, the TPQ(Timer Poll Queue) should be extended to host memory. This patch adds the support of TPQ. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
6b63597d |
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09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Add TSQ link table support In hip08, TSQ(Transport Service Queue) should be extended to host memory to store the doorbells. This patch adds the support of creating TSQ, and then configured to the hardware. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
0b25c9cc |
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28-May-2018 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Fix the illegal memory operation when cross page This patch fixed the potential illegal operation when using the extend sge buffer cross page in post send operation. The bug will cause the calltrace as below. [ 3302.922107] Unable to handle kernel paging request at virtual address ffff00003b3a0004 [ 3302.930009] Mem abort info: [ 3302.932790] Exception class = DABT (current EL), IL = 32 bits [ 3302.938695] SET = 0, FnV = 0 [ 3302.941735] EA = 0, S1PTW = 0 [ 3302.944863] Data abort info: [ 3302.947729] ISV = 0, ISS = 0x00000047 [ 3302.951551] CM = 0, WnR = 1 [ 3302.954506] swapper pgtable: 4k pages, 48-bit VAs, pgd = ffff000009ea5000 [ 3302.961279] [ffff00003b3a0004] *pgd=00000023dfffe003, *pud=00000023dfffd003, *pmd=00000022dc84c003, *pte=0000000000000000 [ 3302.972224] Internal error: Oops: 96000047 [#1] SMP [ 3302.999509] CPU: 9 PID: 19628 Comm: roce_test_main Tainted: G OE 4.14.10 #1 [ 3303.007498] task: ffff80234df78000 task.stack: ffff00000f640000 [ 3303.013412] PC is at hns_roce_v2_post_send+0x690/0xe20 [hns_roce_pci] [ 3303.019843] LR is at hns_roce_v2_post_send+0x658/0xe20 [hns_roce_pci] [ 3303.026269] pc : [<ffff0000020694f8>] lr : [<ffff0000020694c0>] pstate: 804001c9 [ 3303.033649] sp : ffff00000f643870 [ 3303.036951] x29: ffff00000f643870 x28: ffff80232bfa9c00 [ 3303.042250] x27: ffff80234d909380 x26: ffff00003b37f0c0 [ 3303.047549] x25: 0000000000000000 x24: 0000000000000003 [ 3303.052848] x23: 0000000000000000 x22: 0000000000000000 [ 3303.058148] x21: 0000000000000101 x20: 0000000000000001 [ 3303.063447] x19: ffff80236163f800 x18: 0000000000000000 [ 3303.068746] x17: 0000ffff86b76fc8 x16: ffff000008301600 [ 3303.074045] x15: 000020a51c000000 x14: 3128726464615f65 [ 3303.079344] x13: 746f6d6572202c29 x12: 303035312879656b [ 3303.084643] x11: 723a6f666e692072 x10: 573a6f666e693a5d [ 3303.089943] x9 : 0000000000000004 x8 : ffff8023ce38b000 [ 3303.095242] x7 : ffff8023ce38b320 x6 : 0000000000000418 [ 3303.100541] x5 : ffff80232bfa9cc8 x4 : 0000000000000030 [ 3303.105839] x3 : 0000000000000100 x2 : 0000000000000200 [ 3303.111138] x1 : 0000000000000320 x0 : ffff00003b3a0000 [ 3303.116438] Process roce_test_main (pid: 19628, stack limit = 0xffff00000f640000) [ 3303.123906] Call trace: [ 3303.126339] Exception stack(0xffff00000f643730 to 0xffff00000f643870) [ 3303.215790] [<ffff0000020694f8>] hns_roce_v2_post_send+0x690/0xe20 [hns_roce_pci] [ 3303.223293] [<ffff0000021c3750>] rt_ktest_post_send+0x5d0/0x8b8 [rdma_test] [ 3303.230261] [<ffff0000021b3234>] exec_send_cmd+0x664/0x1350 [rdma_test] [ 3303.236881] [<ffff0000021b8b30>] rt_ktest_dispatch_cmd_3+0x1510/0x3790 [rdma_test] [ 3303.244455] [<ffff0000021bae54>] rt_ktest_dispatch_cmd_2+0xa4/0x118 [rdma_test] [ 3303.251770] [<ffff0000021bafec>] rt_ktest_dispatch_cmd+0x124/0xaa8 [rdma_test] [ 3303.258997] [<ffff0000021bbc3c>] rt_ktest_dev_write+0x2cc/0x568 [rdma_test] [ 3303.265947] [<ffff0000082ad688>] __vfs_write+0x60/0x18c [ 3303.271158] [<ffff0000082ad998>] vfs_write+0xa8/0x198 [ 3303.276196] [<ffff0000082adc7c>] SyS_write+0x6c/0xd4 [ 3303.281147] Exception stack(0xffff00000f643ec0 to 0xffff00000f644000) [ 3303.287573] 3ec0: 0000000000000003 0000fffffc85faa8 0000000000004e60 0000000000000000 [ 3303.295388] 3ee0: 0000000021fb2000 000000000000ffff eff0e3efe4e58080 0000fffffcc724fe [ 3303.303204] 3f00: 0000000000000040 1999999999999999 0101010101010101 0000000000000038 [ 3303.311019] 3f20: 0000000000000005 ffffffffffffffff 0d73757461747320 ffffffffffffffff [ 3303.318835] 3f40: 0000000000000000 0000000000459b00 0000fffffc85e360 000000000043d788 [ 3303.326650] 3f60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 3303.334465] 3f80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 3303.342281] 3fa0: 0000000000000000 0000fffffc85e570 0000000000438804 0000fffffc85e570 [ 3303.350096] 3fc0: 0000ffff8553f618 0000000080000000 0000000000000003 0000000000000040 [ 3303.357911] 3fe0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 3303.365729] [<ffff000008083808>] __sys_trace_return+0x0/0x4 [ 3303.371288] Code: b94008e9 34000129 b9400ce2 110006b5 (b9000402) [ 3303.377377] ---[ end trace fd5ab98b3325cf9a ]--- Reported-by: Jie Chen <chenjie103@huawei.com> Reported-by: Xiping Zhang (Francis) <zhangxiping3@huawei.com> Fixes: b1c158350968("RDMA/hns: Get rid of virt_to_page and vmap calls after dma_alloc_coherent") Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
d59fcacc |
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23-May-2018 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Increase checking CMQ status timeout value This patch increases checking CMQ status timeout value and uses the same value with NIC driver to avoid deficiency of time. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
cc3391cb |
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22-May-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Rename the idx field of db The lower 15 bit of paramter of db structure means different meanings when db type is sq, rq and srq. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
9b44703d |
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09-Mar-2018 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Support cq record doorbell for the user space This patch updates to support cq record doorbell for the user space. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
8b9b8d14 |
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05-Feb-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Fix the endian problem for hns The hip06 and hip08 run on a little endian ARM, it needs to revise the annotations to indicate that the HW uses little endian data in the various DMA buffers, and flow the necessary swaps throughout. The imm_data use big endian mode. The cpu_to_le32/le32_to_cpu swaps are no-op for this, which makes the only substantive change the handling of imm_data which is now mandatory swapped. This also keep match with the userspace hns driver and resolve the warning by sparse. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
2eade675 |
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09-Jan-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Update the verbs of polling for completion If the port is a RoCEv2 port, the remote port address and QP information which returned for UD will be modified. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
7bdee415 |
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09-Jan-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Fill sq wqe context of ud type in hip08 This patch mainly configure the fields of sq wqe of ud type when posting wr of gsi qp type. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
ccb8a29e |
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11-Jan-2018 |
Jason Gunthorpe <jgg@ziepe.ca> |
RDMA/hns: Fix endian problems around imm_data and rkey This matches the changes made recently to the userspace hns driver when it was made sparse clean. See rdma-core commit bffd380cfe56 ("libhns: Make the provider sparse clean") wc->imm_data is not used in the kernel so this change has no practical impact. Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
a5073d60 |
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14-Nov-2017 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Add eq support of hip08 This patch adds eq support for hip08. The eq table can be multi-hop addressed. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Reviewed-by: Lijun Ou <oulijun@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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#
b5fddb7c |
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10-Nov-2017 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Add sq_invld_flg field in QP context In hip08 RoCE, it need to add the sq_invld_flg field in QP context for RoCE hardware. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
befb63b4 |
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10-Nov-2017 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Set sq_cur_sge_blk_addr field in QPC in hip08 If the extend sges exist, the sq_cur_sge_blk_addr field in QPC (qp context) should be configured. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
e92f2c18 |
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10-Nov-2017 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Configure TRRL field in hip08 RoCE device The TRRL(Target RDMA Read/aTOMIC List) record the information of receiving RDMA READ or ATOMIC operation in hip08. It will be used the hardware. The driver need to assign a continuous physical address for trrl_ba field of qp context. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
b5ff0f61 |
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26-Oct-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Configure sgid type for hip08 RoCE The hardware vendors need to generate RoCEv1 or RoCEv2 packet according to the sgid type configured. Besides, update the gid table size for hip08 RoCE device. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
3180236c |
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18-Oct-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Update the PD&CQE&MTT specification in hip08 This patch updates the PD specification to 16M for hip08. And it updates the numbers of mtt and cqe segments for the buddy. As the CQE supports hop num 1 addressing, the CQE specification is 64k. This patch updates to set the CQE specification to 64k. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
29a1fe5d |
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18-Oct-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Update the IRRL table chunk size in hip08 As the increase of the IRRL specification in hip08, the IRRL table chunk size needs to be updated. This patch updates the IRRL table chunk size to 256k for hip08. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
3958cc56 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Configure the MTPT in hip08 The MTPT records the attribute of the registered MR. The MTPT format will be updated in hip08, and the MTPT should be configured. This patch is to configure the MTPT for the registered MR in hip08. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
2d407888 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add support for processing send wr and receive wr This patch is implementing for posting send request and receiving request for hip08 RoCE driver. such as post send verbs and post recv verbs. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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#
926a01dc |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add QP operations support for hip08 SoC This patch implements QP operations for hip08 RoCE driver and fixes some checkpatch warning about print message in QP function. The QP operations includes create QP, query QP, modify QP and destroy QP. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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93aa2187 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add CQ operations support for hip08 RoCE driver This patch adds CQ relevant operations for hip08 RoCE driver, such as create CQ, destroy CQ, poll CQ and Request Completion Notification(req_notify_cq). Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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7afddafa |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Configure mac&gid and user access region for hip08 RoCE driver In hip08, the user access region(UAR) pfn is calculated from pci device memory resource. This patch mainly sets mac and gid table by configuring the relevant registers and updates the uar pfn for hip08 SoC. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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ff795f71 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Support multi hop addressing for PBL in hip08 The block base address in the MR can be retrieved by the block number which is calculated with the VA in the SGE and MTPT. In hip08, the PBL supports multi hop addressing to retrieve the block base address by the block number. This patch is to add the interfaces in the MR to support multi hop addressing for the PBL. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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6a93c77a |
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30-Aug-2017 |
Shaobo Xu <xushaobo2@huawei.com> |
RDMA/hns: Update the interfaces for MTT/CQE multi hop addressing in hip08 The MTT(SQWQE/SGE/RQWQE) and CQE in hip08 can support multi hop addressing. The address of MTT/CQE can be retrieved by the BT (Base Address Table) with multi hop addressing. This patch is to update the interfaces in HEM to support multi hop addressing for the MTT/CQE. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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a81fba28 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Configure BT BA and BT attribute for the contexts in hip08 BT is used to retrieve the addresses of the contexts(QPC/MPT/CQC/SRQC) in memory. In order to support multi hop addressing for the contexts, the BT BA should be configured by mailbox, and the BT attribution will be set by command. This patch is to configure the BT BA and BT attribution for the contexts. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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a25d13cb |
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30-Aug-2017 |
Shaobo Xu <xushaobo2@huawei.com> |
RDMA/hns: Add the interfaces to support multi hop addressing for the contexts in hip08 The contexts (QPC/MTPT/CQC/SRQC) in hip08 can support multi hop addressing. The address of context can be retrieved by the BT (Base Address Table) with multi hop addressing. The first hop BT BA can be retrieved from the RAM in the chip by the bt_idx and bt_num. This patch is to add the interfaces in HEM to support multi hop addressing for the contexts. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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a680f2f3 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add mailbox's implementation for hip08 RoCE driver In hip08 SoC, the hardware implementation of mailbox command has changed with hip06 SoC. As a result, it adjusts the architecture of the command code and implements the interfaces of mailbox for hip08 SoC. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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cfc85f3e |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add profile support for hip08 driver The profile's content mainly set some specifications and obtain some hardware resources by implementing the relative commands. Because max sge num of send queue is not the same with receive queue in hip08, we modified the calculation of props->max_sge in query_device ops. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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a04ff739 |
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30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add command queue support for hip08 RoCE driver The command queue is the configuration queue. The software configures hardware by filling the commands into command queues. It includes command send queue and receive queue. In hip08 RoCE engine, It supports to configure and query registers by command queue. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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