#
38d22088 |
|
20-Dec-2021 |
Chengchang Tang <tangchengchang@huawei.com> |
RDMA/hns: Remove support for HIP06 HIP06 is no longer supported. In order to reduce unnecessary maintenance, the code of HIP06 is removed. Link: https://lore.kernel.org/r/20211220130558.61585-1-liangwenpeng@huawei.com Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
a762fe65 |
|
21-Jun-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Add hr_reg_write_bool() In order to avoid to do bitwise operations on a boolean value, add a new register interface to avoid sparse comlaint about "dubious: x & !y" when calling hr_reg_write(ctx, field, !!val). Fixes: dc504774408b ("RDMA/hns: Use new interface to set MPT related fields") Fixes: 495c24808ce7 ("RDMA/hns: Add XRC subtype in QPC and XRC type in SRQC") Link: https://lore.kernel.org/r/1624262443-24528-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
4511624a |
|
19-May-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Rename CMDQ head/tail pointer to PI/CI The same name represents opposite meanings in new/old driver, it is hard to maintain, so rename them to PI/CI. Link: https://lore.kernel.org/r/1621482876-35780-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
0fb46da0 |
|
06-Apr-2021 |
Xi Wang <wangxi11@huawei.com> |
RDMA/hns: Simplify function's resource related command Use hr_reg_write/read() to simplify codes about configuring function's resource. And because the design of PF/VF fields is same, they can be defined only once. Link: https://lore.kernel.org/r/1617715514-29039-2-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
69455df0 |
|
02-Apr-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Prevent le32 from being implicitly converted to u32 Replace BUILD_BUG_ON_ZERO() with BUILD_BUG_ON() to avoid sparse complaining "restricted __le32 degrades to integer". Link: https://lore.kernel.org/r/1617354454-47840-10-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
292b3352 |
|
07-Feb-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Adjust fields and variables about CMDQ tail/head The register 0x07014 is actually the head pointer of CMDQ, and 0x07010 means tail pointer. Current definitions are confusing, so rename them and related variables. The next_to_use of structure hns_roce_v2_cmq_ring has the same semantics as head, merge them into one member. The next_to_clean of structure hns_roce_v2_cmq_ring has the same semantics as tail. After deleting next_to_clean, tail should also be deleted. Link: https://lore.kernel.org/r/1612688143-28226-5-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
dc504774 |
|
23-Jan-2021 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Use new interface to set MPT related fields Achieve hr_reg_write() to simply the codes to fill fields. Link: https://lore.kernel.org/r/1611395282-991-4-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
dcdc366a |
|
10-Dec-2020 |
Wenpeng Liang <liangwenpeng@huawei.com> |
RDMA/hns: Fix incorrect symbol types Types of some fields, variables and parameters of some functions should be unsigned. Link: https://lore.kernel.org/r/1607650657-35992-10-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
bfefae9f |
|
26-Nov-2020 |
Lang Cheng <chenglang@huawei.com> |
RDMA/hns: Add support for CQ stash Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. It can be used to improve the performance by increasing the hit ratio of L3 cache. CQs need to enable stash by default. Link: https://lore.kernel.org/r/1606374251-21512-2-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
|
#
b9c93e3a |
|
20-May-2020 |
Yangyang Li <liyangyang20@huawei.com> |
RDMA/hns: Remove unused code about assert The codes related to assert are no longer used and need to be deleted. Link: https://lore.kernel.org/r/1589982799-28728-5-git-send-email-liweihang@huawei.com Signed-off-by: Yangyang Li <liyangyang20@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
57425822 |
|
04-Apr-2019 |
Leon Romanovsky <leon@kernel.org> |
RDMA/hns: Remove asynchronic QP destroy Verbs destroy callbacks are synchronous operations and can't be delayed. The expectation is that after driver returned from destroy function, the memory can be freed and user won't be able to access it again. Ditch workqueue implementation used in HNS driver. Fixes: d838c481e025 ("IB/hns: Fix the bug when destroy qp") Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Acked-by: oulijun <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
f747b689 |
|
08-Dec-2018 |
Lijun Ou <oulijun@huawei.com> |
RDMA/hns: Update posting & querying mailbox This patch updates the implementation of the mailbox command interface by using command queue instead of operating registers. With this update, the software can be well decoupled with the hardware. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
e8e8b652 |
|
09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Update the implementation of set_mac This patch updates the implementation of set_mac by using command queue instead of directly writing registers. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
4db134a3 |
|
09-Jul-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Update the implementation of set_gid This patch updates the implementation of set_gid by using command queue instead of directly writing registers. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
8b9b8d14 |
|
05-Feb-2018 |
oulijun <oulijun@huawei.com> |
RDMA/hns: Fix the endian problem for hns The hip06 and hip08 run on a little endian ARM, it needs to revise the annotations to indicate that the HW uses little endian data in the various DMA buffers, and flow the necessary swaps throughout. The imm_data use big endian mode. The cpu_to_le32/le32_to_cpu swaps are no-op for this, which makes the only substantive change the handling of imm_data which is now mandatory swapped. This also keep match with the userspace hns driver and resolve the warning by sparse. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
a5073d60 |
|
14-Nov-2017 |
Yixian Liu <liuyixian@huawei.com> |
RDMA/hns: Add eq support of hip08 This patch adds eq support for hip08. The eq table can be multi-hop addressed. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Reviewed-by: Lijun Ou <oulijun@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
7afddafa |
|
30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Configure mac&gid and user access region for hip08 RoCE driver In hip08, the user access region(UAR) pfn is calculated from pci device memory resource. This patch mainly sets mac and gid table by configuring the relevant registers and updates the uar pfn for hip08 SoC. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
a680f2f3 |
|
30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add mailbox's implementation for hip08 RoCE driver In hip08 SoC, the hardware implementation of mailbox command has changed with hip06 SoC. As a result, it adjusts the architecture of the command code and implements the interfaces of mailbox for hip08 SoC. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
a04ff739 |
|
30-Aug-2017 |
Wei Hu(Xavier) <xavier.huwei@huawei.com> |
RDMA/hns: Add command queue support for hip08 RoCE driver The command queue is the configuration queue. The software configures hardware by filling the commands into command queues. It includes command send queue and receive queue. In hip08 RoCE engine, It supports to configure and query registers by command queue. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
afb6b092 |
|
29-Nov-2016 |
Shaobo Xu <xushaobo2@huawei.com> |
IB/hns: Fix the bug when free cq If the resources of cq are freed while executing the user case, hardware can not been notified in hip06 SoC. Then hardware will hold on when it writes the cq buffer which has been released. In order to slove this problem, RoCE driver checks the CQE counter, and ensure that the outstanding CQE have been written. Then the cq buffer can be released. Signed-off-by: Shaobo Xu <xushaobo2@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
d838c481 |
|
29-Nov-2016 |
Wei Hu (Xavier) <xavier.huwei@huawei.com> |
IB/hns: Fix the bug when destroy qp If send queue is still working when qp is in reset state by modify qp in destroy qp function, hardware will hold on and don't work in hip06 SoC. In current codes, RoCE driver check hardware pointer of sending and hardware pointer of processing to ensure that hardware has processed all the dbs of this qp. But while the environment of wire becomes not good, The checking time maybe too long. In order to solve this problem, RoCE driver created a workqueue at probe function. If there is a timeout when checking the status of qp, driver initialize work entry and push it into the workqueue, Work function will finish checking and release the related resources later. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Dongdong Huang(Donald) <hdd.huang@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
8f3e9f3e |
|
23-Nov-2016 |
Wei Hu (Xavier) <xavier.huwei@huawei.com> |
IB/hns: Add code for refreshing CQ CI using TPTR This patch added the code for refreshing CQ CI using TPTR in hip06 SoC. We will send a doorbell to hardware for refreshing CQ CI when user succeed to poll a cqe. But it will be failed if the doorbell has been blocked. So hardware will read a special buffer called TPTR to get the lastest CI value when the cq is almost full. This patch support the special CI buffer as follows: a) Alloc the memory for TPTR in the hns_roce_tptr_init function and free it in hns_roce_tptr_free function, these two functions will be called in probe function and in the remove function. b) Add the code for computing offset(every cq need 2 bytes) and write the dma addr to every cq context to notice hardware in the function named hns_roce_v1_write_cqc. c) Add code for mapping TPTR buffer to user space in function named hns_roce_mmap. The mapping distinguish TPTR and UAR of user mode by vm_pgoff(0: UAR, 1: TPTR, others:invaild) in hip06. d) Alloc the code for refreshing CQ CI using TPTR in the function named hns_roce_v1_poll_cq. e) Add some variable definitions to the related structure. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Dongdong Huang(Donald) <hdd.huang@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
9a443537 |
|
21-Jul-2016 |
oulijun <oulijun@huawei.com> |
IB/hns: Add driver files for hns RoCE driver These are the various new source code files for the Hisilicon RoCE driver for ARM architecture. Signed-off-by: Wei Hu <xavier.huwei@huawei.com> Signed-off-by: Nenglong Zhao <zhaonenglong@hisilicon.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|