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3ea5b370 |
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08-Aug-2022 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
iio: frequency: adf4371: Benefit from devm_clk_get_enabled() to simplify Make use of devm_clk_get_enabled() to replace some code that effectively open codes this new function. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220808204740.307667-10-u.kleine-koenig@pengutronix.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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0bb5675b |
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08-May-2022 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
iio: frequency: adf4371: Fix alignment for DMA safety ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 7f699bd14913 ("iio: frequency: adf4371: Add support for ADF4371 PLL") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-68-jic23@kernel.org
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d3be8324 |
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22-May-2020 |
Alexandru Ardelean <alexandru.ardelean@analog.com> |
iio: remove explicit IIO device parent assignment This patch applies the semantic patch: @@ expression I, P, SP; @@ I = devm_iio_device_alloc(P, SP); ... - I->dev.parent = P; It updates 302 files and does 307 deletions. This semantic patch also removes some comments like '/* Establish that the iio_dev is a child of the i2c device */' But this is is only done in case where the block is left empty. The patch does not seem to cover all cases. It looks like in some cases a different variable is used in some cases to assign the parent, but it points to the same reference. In other cases, the block covered by ... may be just too big to be covered by the semantic patch. However, this looks pretty good as well, as it does cover a big bulk of the drivers that should remove the parent assignment. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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82a5008a |
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05-Aug-2019 |
Nuno Sá <nuno.sa@analog.com> |
iio: frequency: adf4371: Fix output frequency setting The fract1 word was not being properly programmed on the device leading to wrong output frequencies. Fixes: 7f699bd14913 (iio: frequency: adf4371: Add support for ADF4371 PLL) Signed-off-by: Nuno Sá <nuno.sa@analog.com> Reviewed-by: Stefan Popa <stefan.popa@analog.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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def914a4 |
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24-Jun-2019 |
Stefan Popa <stefan.popa@analog.com> |
iio: frequency: adf4371: Add support for output stage mute Another feature of the ADF4371/ADF4372 is that the supply current to the RF8P and RF8N output stage can shut down until the ADF4371 achieves lock as measured by the digital lock detect circuitry. The mute to lock detect bit (MUTE_LD) in REG25 enables this function. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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13a0af41 |
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24-Jun-2019 |
Stefan Popa <stefan.popa@analog.com> |
iio: frequency: adf4371: Add support for ADF4372 PLL The ADF4372 is part of the same family with ADF4371, the main difference is that it has only 3 channels instead of 4, as the frequency quadrupler is missing. As a result, the ADF4372 allows frequencies from 62.5 MHz to 16 GHz to be generated. Datasheet: Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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7f699bd1 |
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04-Jun-2019 |
Stefan Popa <stefan.popa@analog.com> |
iio: frequency: adf4371: Add support for ADF4371 PLL The ADF4371 is a frequency synthesizer with an integrated voltage controlled oscillator (VCO) for phase-locked loops (PLLs). The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. The driver takes the reference input frequency from the device tree and uses it to calculate and maximize the PFD frequency (frequency of the phase frequency detector). The PFD frequency is further used to calculate the timeouts: synthesizer lock, VCO band selection, automatic level calibration (ALC) and PLL settling time. This initial driver exposes the attributes for setting the frequency and enabling/disabling the different adf4371 channels. Datasheet: Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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