#
ff46a601 |
|
05-Jul-2022 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Raptor Lake-S CPU support Add support for the Trace Hub in Raptor Lake-S CPU. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@kernel.org> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20220705082637.59979-7-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
23e2de58 |
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05-Jul-2022 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Raptor Lake-S PCH support Add support for the Trace Hub in Raptor Lake-S PCH. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@kernel.org> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20220705082637.59979-6-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
802a9a0b |
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05-Jul-2022 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Meteor Lake-P support Add support for the Trace Hub in Meteor Lake-P. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@kernel.org> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20220705082637.59979-5-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
086c28ab |
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05-Jul-2022 |
Christophe JAILLET <christophe.jaillet@wanadoo.fr> |
intel_th: Fix a resource leak in an error handling path If an error occurs after calling 'pci_alloc_irq_vectors()', 'pci_free_irq_vectors()' must be called as already done in the remove function. Fixes: 7b7036d47c35 ("intel_th: pci: Use MSI interrupt signalling") Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20220705082637.59979-2-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
48cb1753 |
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14-Apr-2021 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Alder Lake-M support This adds support for the Trace Hub in Alder Lake-M PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20210414171251.14672-8-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
9f7f2a5e |
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14-Apr-2021 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Rocket Lake CPU support This adds support for the Trace Hub in Rocket Lake CPUs. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@vger.kernel.org> # v4.14+ Link: https://lore.kernel.org/r/20210414171251.14672-7-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
a525ed17 |
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14-Apr-2021 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Constify all drvdata references Anything that deals with drvdata structures should leave them intact. Reflect this in function signatures. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210414171251.14672-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
cb5c681a |
|
15-Jan-2021 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Alder Lake-P support This adds support for the Trace Hub in Alder Lake-P. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20210115195917.3184-3-alexander.shishkin@linux.intel.com Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
9f126c56 |
|
05-Oct-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Alder Lake CPU support This adds support for the Trace Hub in Alder Lake CPU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20201005071319.78508-9-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
951e4d71 |
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05-Oct-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Alder Lake-S support This adds support for the Trace Hub in Alder Lake-S. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20201005071319.78508-8-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
fd73d74a |
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06-Jul-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Emmitsburg PCH support This adds support for the Trace Hub in Emmitsburg PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20200706161339.55468-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
6227585d |
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06-Jul-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Tiger Lake PCH-H support This adds support for the Trace Hub in Tiger Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20200706161339.55468-3-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
203c1f61 |
|
06-Jul-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Jasper Lake CPU support This adds support for the Trace Hub in Jasper Lake CPU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20200706161339.55468-2-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
add492d2 |
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17-Mar-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Elkhart Lake CPU support This adds support for the Trace Hub in Elkhart Lake CPU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200317062215.15598-7-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
397c7729 |
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17-Mar-2020 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Disallow multi mode on devices where it's broken Some versions of Intel TH have an issue that prevents the multi mode of MSU from working correctly, resulting in no trace data and potentially stuck MSU pipeline. Disable multi mode on such devices. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200317062215.15598-2-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
88385866 |
|
17-Dec-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Elkhart Lake SOC support This adds support for Intel Trace Hub in Elkhart Lake. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191217115527.74383-3-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e4de2a5d |
|
17-Dec-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Comet Lake PCH-V support This adds Intel(R) Trace Hub PCI ID for Comet Lake PCH-V. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20191217115527.74383-2-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
6e6c18bc |
|
20-Nov-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Tiger Lake CPU support This adds support for the Trace Hub in Tiger Lake CPU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191120130806.44028-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
6a174342 |
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20-Nov-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Ice Lake CPU support This adds support for the Trace Hub in Ice Lake CPU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191120130806.44028-3-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
9d55499d |
|
28-Oct-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Jasper Lake PCH support This adds support for Intel TH on Jasper Lake PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191028070651.9770-8-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
3adbb571 |
|
28-Oct-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Comet Lake PCH support This adds support for Intel TH on Comet Lake PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191028070651.9770-7-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
9c78255f |
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21-Aug-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Tiger Lake support This adds support for the Trace Hub in Tiger Lake PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20190821074955.3925-5-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
164eb56e |
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21-Aug-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add support for another Lewisburg PCH Add support for the Trace Hub in another Lewisburg PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org # v4.14+ Link: https://lore.kernel.org/r/20190821074955.3925-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
4aa5aed2 |
|
21-Jun-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Ice Lake NNPI support This adds Ice Lake NNPI support to the Intel(R) Trace Hub. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20190621161930.60785-5-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
4c5bb6eb |
|
03-May-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Only report useful IRQs to subdevices The only type of IRQ triggering event that is useful to us at the moment is the "last block" interrupt of the MSU. This interrupt can only be enabled via "MINTCTL" register that doesn't exist in earlier version of the Intel TH. Enumerate the presence of MINTCTL via per-device driver data structure and only instantiate the IRQ resource for subdevices if this capability is present. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
7b7036d4 |
|
03-May-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Use MSI interrupt signalling Since Intel TH is capable of MSI interrupt signalling, make use of it. The way it works is, each of the 7 interrupt triggering events has its own vector in this mode, as opposed to interrupt line delivery, where all events are signalled via the same line. Failing to enable MSI, the driver falls back to using an interrupt line. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
62a59302 |
|
03-May-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Communicate IRQ via resource Currently, the IRQ is passed between the glue layers and the core as a separate argument, while the MMIO resources are passed as resources. This also limits the number of IRQs thus used to one, while the current versions of Intel TH use a different MSI vector for each interrupt triggering event, of which there are 7. Change this to pass IRQ in the resources array. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
fc027f4c |
|
03-May-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Add "rtit" source device In some versions of Intel TH, the Software Trace Hub (STH) has a second MMIO BAR dedicated to the input from Intel PT. This calls for a new subdevice that will be enumerated if the corresponding BAR is present. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
db73a059 |
|
03-May-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Rework resource passing between glue layers and core Currently, MMIO resource numbers in the TH driver core correspond to PCI BAR numbers, because in the beginning there was only the PCI glue layer. This created some confusion when the ACPI glue layer was added. To avoid confusion and remove glue-specific code from the driver core, split the resource indices between core and glue layers and change the API so that the driver core receives the MMIO resources in the same fixed order. At the same time, make the IRQ always be a parameter to intel_th_alloc() instead of sometimes passing it as a resource. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
e60e9a4b |
|
17-Apr-2019 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Comet Lake support This adds support for Intel TH on Comet Lake. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
59d08d00 |
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18-Sep-2018 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Ice Lake PCH support This adds Intel(R) Trace Hub PCI ID for Ice Lake PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
50352fa7 |
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28-Mar-2018 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate This adds SPDX GPL-2.0 header to the Trace Hub driver and removes the GPLv2 boilerplate text. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
24600840 |
|
19-Sep-2017 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Lewisburg PCH support This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
920ce7c3 |
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19-Sep-2017 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Cedar Fork PCH support This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
a0e7df33 |
|
24-Feb-2017 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Perform time resync on capture start On some devices (TH 2.x devices at the moment), the internal time counter is initially not synchronized to the global crystal clock, so the time stamps it produces will not be useful. In this case, the driver needs to force the time counter resync. This applies the workaround to relevant devices. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
3321371b |
|
18-Aug-2017 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Use drvdata for quirks Allow attaching miscellaneous quirk information to devices as drvdata. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
efb3669e |
|
30-Jun-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Cannon Lake PCH-LP support This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
|
#
84331e13 |
|
30-Jun-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Cannon Lake PCH-H support This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
|
#
e9b2b3e7 |
|
10-Aug-2017 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Enable bus mastering The driver forgets to enable bus mastering for the PCI device. Fix this. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
340837f9 |
|
30-Jun-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Gemini Lake support This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
5118ccd3 |
|
08-Sep-2015 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Denverton SOC support This adds Intel(R) Trace Hub PCI ID for Denverton SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
#
7a1a47ce |
|
28-Jun-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Kaby Lake PCH-H support This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
|
#
aaa3ca82 |
|
08-Apr-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Broxton-M SOC support This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Laurent Fert <laurent.fert@intel.com>
|
#
d7b17871 |
|
15-Feb-2016 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Set root device's drvdata early Already during the subdevice initialization time, devices will need to reference Intel TH controller descriptor structure. This patch moves setting the drvdata from the pci glue to intel_th core, before subdevices are populated. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
3f040887 |
|
22-Dec-2015 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Broxton SOC support This adds Intel(R) Trace Hub PCI ID for Broxton SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
6396b912 |
|
22-Dec-2015 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: pci: Add Apollo Lake SOC support This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
2b0b16d3 |
|
22-Sep-2015 |
Alexander Shishkin <alexander.shishkin@linux.intel.com> |
intel_th: Add pci glue layer for Intel(R) Trace Hub This patch adds basic support for PCI-based Intel TH devices. It requests 2 bars (configuration registers for the subdevices and STH channel MMIO region) and calls into Intel TH core code to create the bus with subdevices etc. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|